TN2524
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
►
Low threshold — 2.0V max
►
►
►
►
High input impedance
Low input capacitance — 125pF max
Fast switching speeds
Low ON-resistance
General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input impedance
and positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
►
Free from secondary breakdown
►
Low input and output leakage
►
Complementary N and P-channel devices
Applications
►
►
►
►
►
►
►
Logic level interfaces — ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic devices
Analog switches
General purpose line drivers
Telecom switches
Ordering Information
BV
DSS
/BV
DGS
(V)
R
DS(ON)
max
(Ω)
V
GS(th)
max
(V)
I
D(ON)
min
(A)
Package Options
TO-243AA (SOT-89)
TN2524N8-G
Die*
TN2524ND
240
6.0
2.0
1.0
-G indicates package is RoHS compliant (‘Green’)
* MIL visual screening available.
Pin Configuration
DRAIN
Absolute Maximum Ratings
Parameter
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
Operating and storage temperature
Soldering temperature*
Value
BV
DSS
BV
DGS
±20V
-55
O
C to +150
O
C
300
O
C
DRAIN
GATE
SOURCE
TO-243AA (SOT-89) (N8)
Product Marking
TN5CW
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
W = Code for week sealed
TO-243AA (SOT-89) (N8)
TN2524
Thermal Characteristics
Package
TO-243AA (SOT-89)
(continuous)
(A)
I
D
*
(pulsed)
(A)
I
D
Power Dissipation
@T
A
= 25
O
C
(W)
θ
jc
( C/W)
O
θ
ja
( C/W)
O
I
DR
*
(A)
I
DRM
(A)
0.36
2.0
1.6
(†)
15
78
(†)
0.36
2.0
Notes:
* I
D
(continuous) is limited by max rated T
j
.
† Mounted on FR5 board, 25mm x 25mm x 1.57mm.
Electrical Characteristics
(T
Sym
BV
DSS
V
GS(th)
ΔV
GS(th)
I
GSS
I
DSS
Parameter
A
= 25
O
C unless otherwise specified)
Min
240
0.6
-
-
-
Typ
-
-
-
-
-
-
1.9
2.8
4.0
4.0
-
600
65
35
10
-
-
-
-
-
300
Max
-
2.0
-5.0
100
10
1.0
-
-
6.0
6.0
1.4
-
125
70
25
10
10
20
20
1.8
-
Units
V
V
nA
µA
mA
A
Ω
%/
O
C
Conditions
V
GS
= 0V, I
D
= 2.0mA
V
GS
= V
DS
, I
D
= 1.0mA
V
GS
= ± 20V, V
DS
= 0V
V
GS
= 0V, V
DS
= Max Rating
V
GS
= 0V, V
DS
= 0.8 Max Rat-
ing, T
A
= 125°C
V
GS
= 4.5V, V
DS
= 25V
V
GS
= 10V, V
DS
= 25V
V
GS
= 4.5V, I
D
= 250mA
V
GS
= 10, I
D
= 0.5A
V
GS
= 10V, I
D
= 0.5A
V
GS
= 0V,
V
DS
= 25V,
f = 1.0MHz
V
DD
= 25V,
I
D
= 1.0A,
R
GEN
= 25Ω
Drain-to-source breakdown voltage
Gate threshold voltage
Change in V
GS(th)
with temperature
Gate body leakage
Zero gate voltage drain current
mV/
O
C V
GS
= V
DS
, I
D
= 1.0mA
-
0.5
1.0
-
-
-
300
-
-
-
-
-
-
-
-
-
I
D(ON)
R
DS(ON)
ΔR
DS(ON)
G
FS
C
ISS
C
OSS
C
RSS
t
d(ON)
t
r
t
d(OFF)
t
f
V
SD
t
rr
ON-state drain current
Static drain-to-source ON-state resistance
Change in R
DS(ON)
with temperature
Forward transductance
Input capacitance
Common source output capacitance
Reverse transfer capacitance
Turn-ON delay time
Rise time
Turn-OFF delay time
Fall time
Diode forward voltage drop
Reverse recovery time
mmho V
DS
= 25V, I
D
= 0.5A
pF
ns
V
ns
V
GS
= 0V, I
SD
= 1.0A
V
GS
= 0V, I
SD
= 1.0A
Notes:
(1) All D.C. parameters 100% tested at 25
O
C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
(2) All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
V
DD
10V
90%
INPUT
0V
10%
t
(ON)
PULSE
GENERATOR
t
(OFF)
t
r
t
d(OFF)
t
F
R
L
OUTPUT
R
GEN
t
d(ON)
V
DD
10%
10%
INPUT
D.U.T.
OUTPUT
0V
90%
90%
2
TN2524
Typical Performance Curves
(cont.)
BV
DSS
Variation with Temperature
10
1.1
8
On-Resistance vs. Drain Current
V
GS
= 4.5V
V
GS
= 10V
BV
DSS
(normalized)
R
DS(ON)
(ohms)
-50
0
50
100
150
6
1.0
4
2
0.9
0
0
1
2
3
4
5
T
j
(
°
C)
Transfer Characteristics
3.0
I
D
(amperes)
V
(th)
and R
DS
Variation with Temperature
2.4
1.4
V
DS
= 25V
2.5
25°C
1.2
I
D
(amperes)
2.0
V
(th)
@ 1mA
1.0
1.6
1.5
1.2
0.8
0.8
1.0
0.5
0.6
0
0
2
4
6
8
10
-50
0
50
100
150
0.4
V
GS
(volts)
Capacitance vs. Drain-to-Source Voltage
200
10
T
j
(
°
C)
Gate Drive Dynamic Characteristics
f = 1MHz
8
150
V
DS
= 10V
C (picofarads)
V
GS
(volts)
6
100
V
DS
= 40V
4
150 pF
C
ISS
50
C
OSS
C
RSS
0
0
10
20
30
40
2
0
0
0.4
63pF
0.8
1.2
1.6
2.0
V
DS
(volts)
Q
G
(nanocoulombs)
4
R
DS(ON)
(normalized)
V
GS(th)
(normalized)
T
A
= -55°C
150°C
R
DS(ON)
@ 10V, 0.5A
2.0
TN2524
3-Lead TO-243AA (SOT-89) Package Outline (N8)
D
D1
4
C
E H
E1
1
L
b
e
2
3
b1
e1
A
Top View
Side View
Symbol
MIN
Dimensions
(mm)
NOM
MAX
A
1.40
-
1.60
b
0.44
-
0.56
b1
0.36
-
0.48
C
0.35
-
0.44
D
4.40
-
4.60
D1
1.62
-
1.83
E
2.29
-
2.60
E1
2.13
-
2.29
e
1.50
BSC
e1
3.00
BSC
H
3.94
-
4.25
L
0.89
-
1.20
JEDEC Registration TO-243, Variation AA, Issue C, July 1986.
Drawings not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to
http://www.supertex.com/packaging.html.)
Doc.# DSFP-TN2524
A101207
5
Embedded System
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