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74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
Rev. 5 — 29 January 2016
Product data sheet
1. General description
The 74HC175; 74HCT175 is a quad positive-edge triggered D-type flip-flop with individual
data inputs (Dn) and complementary outputs (Qn and Qn). The common clock (CP) and
master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that
meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be
stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flops and
outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Input levels:
For 74HC175: CMOS level
For 74HCT175: TTL level
Four edge-triggered D-type flip-flops
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C.
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC175D
74HCT175D
74HC175DB
74HCT175DB
74HC175PW
74HCT175PW
40 C
to +125
C
TSSOP16
40 C
to +125
C
SSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads; body width
3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1
Type number
NXP Semiconductors
74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram
74HC_HCT175
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 5 — 29 January 2016
2 of 19
NXP Semiconductors
74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
Fig 4.
Pin configuration SO16
Fig 5.
Pin configuration SSOP16 and TSSOP16
5.2 Pin description
Table 2.
Symbol
MR
Q0 to Q3
Q0 to Q3
D0 to D3
GND
CP
V
CC
Pin description
Pin
1
2, 7, 10, 15
3, 6, 11, 14
4, 5, 12, 13
8
9
16
Description
asynchronous master reset input (active LOW)
flip-flop output
complementary flip-flop output
data input
ground (0 V)
clock input (LOW-to-HIGH edge-triggered)
positive supply voltage
74HC_HCT175
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 5 — 29 January 2016
3 of 19
NXP Semiconductors
74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
6. Functional description
Table 3.
Function table
[1]
Inputs
MR
reset (clear)
load “1”
load “0”
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Operating modes
Outputs
CP
X
Dn
X
h
l
Qn
L
H
L
Qn
H
L
H
L
H
H
Fig 6.
Functional diagram
74HC_HCT175
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 5 — 29 January 2016
4 of 19
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