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PT7V4050GKCHA47.457/47.457

Description
Clock Generator,
CategoryMicrocontrollers and processors    The clock generator   
File Size216KB,7 Pages
ManufacturerPericom Semiconductor Corporation (Diodes Incorporated)
Websitehttps://www.diodes.com/
Download Datasheet Parametric View All

PT7V4050GKCHA47.457/47.457 Overview

Clock Generator,

PT7V4050GKCHA47.457/47.457 Parametric

Parameter NameAttribute value
MakerPericom Semiconductor Corporation (Diodes Incorporated)
package instruction,
Reach Compliance Codeunknown
Base Number Matches1
Preliminary Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Features
• PLL with quartz stabilized VCXO
• Loss of signals alarm
• Return to nominal clock upon LOS
• Input data rates from 8 kb/s to 65 Mb/s
• Tri-state output
• User defined PLL loop response
• NRZ data compatible
• Single +5.0V power supply
General Description
The device is composed of a phase-lock loop with an
integrated VCXO for use in clock recovery, data re-
timing, frequency translation and clock smoothing
applications in telecom and datacom systems.
Crystal Frequencies Supported:
12.000~65.536 MHz
Block Diagram
CLKIN
DATAIN
HIZ
Phase Detector &
LossOf Signal
Circuit
RCLK
RDATA
LOS
PHO
VC
LOSIN
CLK1
VCXO
Divider
CLK2
OPOUT
OPN
Op
Amp
OPP
Ordering Information
PT7V4050
Device Type
16-pin clock recovery
Package Leads
T: Thru-Hole
G: Surface Mount
M: Metal Can
CLK2 Divider
A: Divide by 2
E: Div ide by 32
B: Divide by 4
F: Divide by 64
C: Divide by 8
G: Divide by 128
D: Divide by 16
H: Divide by 256
K: Disable
T
B
C
G
A
51.840 / 25.920
CLK2 Frequency
module
CLK1 Frequency
Power Supply
A: 5.0V
C: ± 20ppm
F: ±32ppm
G:
±
50ppm
H:
±
100ppm
Temperature Range
C: 0
°
C to 70
°
C
T: -40
°
C to 85
°
C
12.000
16.128
18.432
22.579
28.000
34.368
44.736
51.840
54.000
Frequencies using at CLK1 (MHz)
12.288
12.624
13.00
16.000
13.384
16.777
16.896
17.920
18.936
20.000
20.480
22.1184
24.586
30.720
38.880
47.457
65.536
60.000
24.704
32.000
40.000
49.152
19.440
61.440
25.000
32.768
41.2416
49.408
35.328
62.208
27.000
33.330
41.943
50.000
40.960
62.500
PT0125(05/03)
1
Ver:0
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