EP7311 Data Sheet
FEATURES
I
ARM720T Processor
— ARM7TDMI CPU
— 8 KB of four-way set-associative cache
— MMU with 64-entry TLB
— Thumb code support enabled
I
Ultra low power
— 90 mW at 74 MHz typical
— 30 mW at 18 MHz typical
— 10 mW in the Idle State
— <1 mW in the Standby State
I
48 KB of on-chip SRAM
I
MaverickKey™ IDs
— 32-bit unique ID can be used for SDMI compliance
— 128-bit random ID
I
Dynamically programmable clock speeds of
18, 36, 49, and 74 MHz
High-Performance,
Low-Power System on Chip with
SDRAM and Enhanced Digital
Audio Interface
OVERVIEW
The Maverick™ EP7311 is designed for ultra-low-power
applications such as PDAs, smart cellular phones, and
industrial hand held information appliances. The core-
logic functionality of the device is built around an
ARM720T processor with 8 KB of four-way set-
associative unified cache and a write buffer. Incorporated
into the ARM720T is an enhanced memory management
unit (MMU) which allows for support of sophisticated
operating systems like Linux
®
.
(cont.)
(cont.)
BLOCK DIAGRAM
Multimedia
Codec Port
Power
Management
EPB Bus
Clocks &
Timers
ARM720T
USER INTERFACE
ICE-JTAG
ARM7TDMI CPU Core
Interrupts,
PWM & GPIO
SERIAL PORTS
Serial
Interface
(2) UARTs
w/ IrDA
Internal Data Bus
8 KB
Cache
Boot
ROM
Write
Buffer
Bus
Bridge
MMU
Keypad&
Touch
Screen I/F
Memory Controller
MaverickKey
TM
SRAM I/F
SDRAM I/F
On-chip SRAM
48 KB
LCD
Controller
MEMORY AND STORAGE
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
http://www.cirrus.com
©
Nov ’03
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
FEATURES
(cont)
I
LCD controller
— Interfaces directly to a single-scan panel
monochrome STN LCD
— Interfaces to a single-scan panel color STN LCD
with minimal external glue logic
I
Full JTAG boundary scan and Embedded ICE
support
I
Integrated Peripheral Interfaces
— 32-bit SDRAM Interface up to 2 external banks
— 8/32/16-bit SRAM/FLASH/ROM Interface
— Multimedia Codec Port
— Two Synchronous Serial Interfaces (SSI1, SSI2)
— CODEC Sound Interface
— 8×8 Keypad Scanner
— 27 General Purpose Input/Output pins
— Dedicated LED flasher pin from the RTC
I
Internal Peripherals
— Two 16550 compatible UARTs
— IrDA Interface
— Two PWM Interfaces
— Real-time Clock
— Two general purpose 16-bit timers
— Interrupt Controller
— Boot ROM
I
Package
— 208-Pin LQFP
— 256-Ball PBGA
— 204-Ball TFBGA
I
The fully static EP7311 is optimized for low power
dissipation and is fabricated on a 0.25 micron CMOS
process
I
Development Kits
— EDB7312: Development Kit with color STN LCD
on board.
— EDB7312-LW: EDB7312 with Lynuxworks’
BlueCat Linux Tools and software for Windows
host (free 30 day BlueCat support from
Lynuxworks).
— EDB7312-LL: EDB7312 with Lynuxworks’ BlueCat
Linux Tools and software for Linux host (free 30
day BlueCat support from Lynuxworks).
Note:
* BlueCat available separately through Lynuxworks
only.
* Use the EDB7312 Development Kit for all the EP73xx
devices.
OVERVIEW
(cont.)
The EP7311 is designed for low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation
range of 2.5 V–3.3 V. The device has three basic power
states: operating, idle and standby.
One of its notable features is MaverickKey unique IDs.
These are factory programmed IDs in response to the
growing concern over secure web content and commerce.
With Internet security playing an important role in the
delivery of digital media such as books or music,
traditional software methods are quickly becoming
unreliable. The MaverickKey unique IDs consist of two
registers, one 32-bit series register and one random 128-
bit register that may be used by an OEM for an
authentication mechanism.
Simply by adding desired memory and peripherals to the
highly integrated EP7311 completes a low-power system
solution. All necessary interface logic is integrated on-
chip.
©
2
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
®
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
Processor Core - ARM720T
The EP7311 incorporates an ARM 32-bit RISC
microcontroller that controls a wide range of on-chip
peripherals. The processor utilizes a three-stage pipeline
consisting of fetch, decode and execute stages. Key
features include:
• ARM (32-bit) and Thumb (16-bit compressed)
instruction sets
• Enhanced MMU for Microsoft Windows CE and other
operating systems
• 8 KB of 4-way set-associative cache.
• Translation Look Aside Buffers with 64 Translated
Entries
Digital Music Initiative) or any other authentication
mechanism.
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7311 through the use of laser
probing technology. These IDs can then be used to match
secure copyrighted content with the ID of the target
device the EP7311 is powering, and then deliver the
copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today’s
Internet appliances.
Memory Interfaces
There are two main external memory interfaces. The first
one is the ROM/SRAM/FLASH-style interface that has
programmable wait-state timings and includes burst-
mode capability, with six chip selects decoding six
256 MB sections of addressable space. For maximum
flexibility, each bank can be specified to be 8-, 16-, or 32-
bits wide. This allows the use of 8-bit-wide boot ROM
options to minimize overall system cost. The on-chip
boot ROM can be used in product manufacturing to
serially download system code into system FLASH
memory. To further minimize system memory
requirements and cost, the ARM Thumb instruction set is
supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industry-
leading code density.
Pin Mnemonic
nCS[5:0]
A[27:0]
Power Management
The EP7311 is designed for ultra-low-power operation.
Its core operates at only 2.5 V, while its I/O has an
operation range of 2.5 V–3.3 V allowing the device to
achieve a performance level equivalent to 60 MIPS. The
device has three basic power states:
• Operating — This state is the full performance
state. All the clocks and peripheral logic are
enabled.
• Idle — This state is the same as the Operating
State, except the CPU clock is halted while
waiting for an event such as a key press.
• Standby — This state is equivalent to the
computer being switched off (no display), and
the main oscillator shut down. An event such as
a key press can wake-up the processor.
I/O
O
O
I/O
Pin Description
Chip select out
Address output
Data I/O
ROM expansion OP enable
ROM expansion write enable
Halfword access select
output
Word access select output
Transfer direction
Pin Mnemonic
BATOK
nEXTPWR
nPWRFL
nBATCHG
I/O
I
I
I
I
Pin Description
Battery ok input
D[31:0]
nMOE/nSDCAS
nMWE/nSDWE
(Note)
(Note)
O
O
O
O
External power supply sense
input
Power fail sense input
HALFWORD
WORD
Battery changed sense input
WRITE/nSDRAS
(Note)
O
Table B. Static Memory Interface Pin Assignments
Table A. Power Management Pin Assignments
MaverickKey
™
Unique ID
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Note:
Pins are multiplexed. See
Table S on page 8
for more
information.
©
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
3
EP7311
High-Performance, Low-Power System on Chip
The second is the programmable 16- or 32-bit-wide
SDRAM interface that allows direct connection of up to
two banks of SDRAM, totaling 512 Mb. To assure the
lowest possible power consumption, the EP7311
supports self-refresh SDRAMs, which are placed in a
low-power state by the device when it enters the low-
power Standby State.
Pin Mnemonic
SDCLK
SDCKE
nSDCS[1:0]
WRITE/nSDRAS
nMOE/nSDCAS
nMWE/nSDWE
A[27:15]/DRA[0:12]
A[14:13]/DRA[12:14]
PD[7:6]/SDQM[1:0]
SDQM[3:2]
D[31:0]
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 1)
RX/TX signals to/from UART 1 to enable these signals
to drive an infrared communication interface directly.
Pin Mnemonic
TXD[1]
RXD[1]
CTS
I/O
O
I
I
I
I
O
I
O
I
Pin Description
UART 1 transmit
UART 1 receive
UART 1 clear to send
UART 1 data carrier detect
UART 1 data set ready
UART 2 transmit
UART 2 receive
Infrared LED drive output
Photo diode input
I/O
O
O
O
O
O
O
O
O
I/O
O
I/O
Pin Description
SDRAM clock output
SDRAM clock enable output
SDRAM chip select out
SDRAM RAS signal output
SDRAM CAS control signal
SDRAM write enable control
signal
SDRAM address
SDRAM internal bank select
SDRAM byte lane mask
SDRAM byte lane mask
Data I/O
DCD
DSR
TXD[2]
RXD[2]
LEDDRV
PHDIN
Table D. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Multimedia Codec Port (MCP)
The Multimedia Codec Port provides access to an audio
codec, a telecom codec, a touchscreen interface, four
general purpose analog-to-digital converter inputs, and
ten programmable digital I/O lines.
Pin Mnemonic
I/O
O
O
I
O
Table C. SDRAM Interface Pin Assignments
Pin Description
Serial bit clock
Serial data out
Serial data in
Sample clock
Note:
1. Pins A[27:13] map to DRA[0:14] respectively.
(i.e. A[27}/DRA[0}, A[26}/DRA[1], etc.) This is to
balance the load for large memory systems.
2. Pins are multiplexed. See
Table S on page 8
for
more information.
SIBCLK
SIBDOUT
SIBDIN
SIBSYNC
Digital Audio Capability
The EP7311 uses its powerful 32-bit RISC processing
engine to implement audio decompression algorithms in
software. The nature of the on-board RISC processor, and
the availability of efficient C-compilers and other
software development tools, ensures that a wide range of
audio decompression algorithms can easily be ported to
and run on the EP7311
Table E. MCP Interface Pin Assignments
Note:
See
Table R on page 8
for information on pin
multiplexes.
Universal Asynchronous
Receiver/Transmitters (UARTs)
The EP7311 includes two 16550-type UARTs for RS-232
serial communications, both of which have two 16-byte
FIFOs for receiving and transmitting data. The UARTs
support bit rates up to 115.2 kbps. An IrDA SIR protocol
encoder/decoder can be optionally switched into the
©
4
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS506PP1
EP7311
High-Performance, Low-Power System on Chip
CODEC Interface
The EP7311 includes an interface to telephony-type
CODECs for easy integration into voice-over-IP and
other voice communications systems. The CODEC
interface is multiplexed to the same pins as the MCP and
SSI2.
Pin Mnemonic
PCMCLK
PCMOUT
PCMIN
PCMSYNC
Synchronous Serial Interface
• ADC (SSI) Interface: Master mode only; SPI and
Microwire1-compatible (128 kbps operation)
• Selectable serial clock polarity
Pin Mnemonic
I/O
O
O
I
O
I/O
O
I
O
O
O
Pin Description
SSI1 ADC serial clock
SSI1 ADC serial input
SSI1 ADC serial output
SSI1 ADC chip select
SSI1 ADC sample clock
Pin Description
ADCLK
Serial bit clock
Serial data out
Serial data in
Frame sync
ADCIN
ADCOUT
nADCCS
SMPCLK
Table F. CODEC Interface Pin Assignments
Note:
See
Table R on page 8
for information on pin
multiplexes.
Table H. Serial Interface Pin Assignments
LCD Controller
A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The
display frame buffer start address is programmable,
allowing the LCD frame buffer to be in SDRAM, internal
SRAM or external SRAM.
• Interfaces directly to a single-scan panel monochrome
STN LCD
• Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
• Panel width size is programmable from 32 to 1024
pixels in 16-pixel increments
• Video frame buffer size programmable up to
128 KB
• Bits per pixel of 1, 2, or 4 bits
SSI2 Interface
An additional SPI/Microwire1-compatible interface is
available for both master and slave mode
communications. The SSI2 unit shares the same pins as
the MCP and CODEC interfaces through a multiplexer.
•
•
•
•
Synchronous clock speeds of up to 512 kHz
Separate 16 entry TX and RX half-word wide FIFOs
Half empty/full interrupts for FIFOs
Separate RX and TX frame sync signals for
asymmetric traffic
Pin Mnemonic
SSICLK
SSITXDA
SSIRXDA
SSITXFR
SSIRXFR
I/O
I/O
O
I
I/O
I/O
Pin Description
Serial bit clock
Serial data out
Serial data in
Transmit frame sync
Receive frame sync
Pin Mnemonic
CL1
CL2
DD[3:0]
FRM
M
I/O
O
O
O
O
O
Pin Description
LCD line clock
LCD pixel clock out
LCD serial display data bus
LCD frame synchronization pulse
LCD AC bias drive
Table G. SSI2 Interface Pin Assignments
Note:
See
Table R on page 8
for information on pin
multiplexes.
Table I. LCD Interface Pin Assignments
©
DS506PP1
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
5
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