70V3319S133BCGI datasheet, PDF

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70V3319S133BCGI: DescriptionCABGA-256, Tray; Categorystorage; File Size459KB，24 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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70V3319S133BCGI Overview

CABGA-256, Tray

70V3319S133BCGI Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	CABGA
package instruction	LBGA, BGA256,16X16,40
Contacts	256
Manufacturer packaging code	BCG256
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Samacsys Description	CHIP ARRAY BGA 17.0 X 1.7.0 MM X 1.0 MM
Maximum access time	4.2 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	S-CBGA-B256
JESD-609 code	e1
length	17 mm
memory density	4718592 bit
Memory IC Type	DUAL-PORT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	256
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX18
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	LBGA
Encapsulate equivalent code	BGA256,16X16,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum standby current	0.04 A
Minimum standby current	3.15 V
Maximum slew rate	0.48 mA
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	17 mm
Base Number Matches	1

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HIGH-SPEED 3.3V

70V3319/99S

256/128K x 18

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

– Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

– Due to limited pin count PL/

option is not supported

on the 128-pin TQFP package. Device is pipelined

outputs only on each port.

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 6ns cycle time, 166MHz operation (6Gbps bandwidth)

– Fast 3.6ns clock to data out

– 1.7ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz

– Data input, address, byte enable and control registers

◆

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output mode

LVTTL- compatible, single 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 133MHz.

Available in a 128-pin Thin Quad Flatpack, 208-pin fine

pitch Ball Grid Array, and 256-pin Ball

Grid Array

Supports JTAG features compliant to IEEE 1149.1

– Due to limited pin count, JTAG is not supported on the

128-pin TQFP package

Green parts available, see ordering information

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

1b 0b

1a 0a

1/0

FT/PIPE

R/W

1/0

B B

1 0

R R

1/0

R/W

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

1b 0b 1a 0a

0a 1a 0b 1b

0/1

FT/PIPE

0/1

256K x 18

MEMORY

ARRAY

I/O

- I/O

17L

Din_L

Din_R

I/O

- I/O

17R

CLK

17L(1)

REPEAT

ADS

CNTEN

CLK

17R(1)

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

5623 tbl 01

NOTE:

1. A

is a NC for IDT70V3399.

TDI

JTAG

TDO

TCK

TMS

TRST

NOVEMBER 2019

DSC

5623/13

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