74VHC161 4-Bit Binary Counter with Asynchronous Clear
August 1993
Revised February 2002
74VHC161
4-Bit Binary Counter with Asynchronous Clear
General Description
The VHC161 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation. The VHC161 is a high-speed synchronous modulo-
16 binary counter. This device is synchronously presettable
for application in programmable dividers and have two
types of Count Enable inputs plus a Terminal Count output
for versatility in forming synchronous multistage counters.
The VHC161 has an asynchronous Master Reset input that
overrides all other inputs and forces the outputs LOW. An
input protection circuit insures that 0V to 7V can be applied
to the input pins without regard to the supply voltage. This
device can be used to interface 5V to 3V systems and two
supply systems such as battery backup. This circuit pre-
vents device destruction due to mismatched supply and
input voltages.
Features
s
High Speed:
f
MAX
=
185 MHz (typ) at T
A
=
25
°
C
s
Synchronous counting and loading
s
High-speed synchronous expansion
s
Low power dissipation:
I
CC
=
4
µ
A (max) at T
A
=
25
°
C
s
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
s
Power down protection provided on all inputs
s
Low noise: V
OLP
=
0.8V (max)
s
Pin and function compatible with 74HC161
Ordering Code:
Order Number
74VHC161M
74VHC161SJ
74VHC161MTC
74VHC161N
Package Number
M16A
M16D
MTC16
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
© 2002 Fairchild Semiconductor Corporation
DS011635
www.fairchildsemi.com
74VHC161
Connection Diagram
Pin Descriptions
Pin Names
CEP
CET
CP
MR
P
0
–P
3
PE
Q
0
–Q
3
TC
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Asynchronous Master Reset Input
Parallel Data Inputs
Parallel Enable Inputs
Flip-Flop Outputs
Terminal Count Output
Functional Description
The VHC161 counts in modulo-16 binary sequence. From
state 15 (HHHH) it increments to state 0 (LLLL). The clock
inputs of all flip-flops are driven in parallel through a clock
buffer. Thus all changes of the Q outputs (except due to
Master Reset of the VHC161) occur as a result of, and syn-
chronous with, the LOW-to-HIGH transition of the CP input
signal. The circuits have four fundamental modes of opera-
tion, in order of precedence: asynchronous reset, parallel
load, count-up and hold. Five control inputs—Master
Reset, Parallel Enable (PE), Count Enable Parallel (CEP)
and Count Enable Trickle (CET)—determine the mode of
operation, as shown in the Mode Select Table. A LOW sig-
nal on MR overrides all other inputs and asynchronously
forces all outputs LOW. A LOW signal on PE overrides
counting and allows information on the Parallel Data (P
n
)
inputs to be loaded into the flip-flops on the next rising
edge of CP. With PE and MR HIGH, CEP and CET permit
counting when both are HIGH. Conversely, a LOW signal
on either CEP or CET inhibits counting.
The VHC161 uses D-type edge-triggered flip-flops and
changing the PE, CEP and CET inputs when the CP is in
either state does not cause errors, provided that the recom-
mended setup and hold times, with respect to the rising
edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement synchro-
nous multistage counters, the TC outputs can be used with
the CEP and CET inputs in two different ways.
Figure 1
shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC
delays of the intermediate stages, plus the CET to CP
setup time of the last stage. This total delay plus setup time
sets the upper limit on clock frequency. For faster clock
rates, the carry lookahead connections shown in
Figure 2
are recommended. In this scheme the ripple delay through
the intermediate stages commences with the same clock
that causes the first stage to tick over from max to min to
start its final cycle. Since this final cycle requires 16 clocks
to complete, there is plenty of time for the ripple to progress
through the intermediate stages. The critical timing that lim-
its the clock period is the CP to TC delay of the first stage
plus the CEP to CP setup time of the last stage. The TC
output is subject to decoding spikes due to internal race
conditions and is therefore not recommended for use as a
clock or asynchronous reset for flip-flops, registers or
counters.
Logic Equations: Count Enable
=
CEP • CET • PE
TC
=
Q
0
• Q
1
• Q
2
• Q
3
• CET
FIGURE 1. Multistage Counter with Ripple Carry
FIGURE 2. Multistage Counter with Lookahead Carry
www.fairchildsemi.com
2
74VHC161
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Input Diode Current (I
IK
)
Output Diode Current (I
OK
)
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
)
Storage Temperature (T
STG
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
0.5V to V
CC
+
0.5V
−
20 mA
±
20 mA
±
25 mA
±
50 mA
−
65
°
C to
+
150
°
C
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Operating Temperature (T
OPR
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
3.3V
±
0.3V
V
CC
=
5.0V
±
0.5V
0
∼
100 ns/V
0
∼
20 ns/V
2.0V to
+
5.5V
0V to
+
5.5V
0V to V
CC
−
40
°
C to
+
85
°
C
Note 1:
Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level
Input Voltage
LOW Level
Input Voltage
HIGH Level
Output Voltage
V
CC
(V)
2.0
3.0
−
5.5
2.0
3.0
−
5.5
2.0
3.0
4.5
3.0
4.5
V
OL
LOW Level
Output Voltage
2.0
3.0
4.5
3.0
4.5
I
IN
I
CC
Input Leakage Current
Quiescent Supply Current
0
−
5.5
5.5
1.9
2.9
4.4
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
±0.1
4.0
2.0
3.0
4.5
T
A
=
25°C
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
1.9
2.9
4.4
2.48
3.80
0.1
0.1
0.1
0.44
0.44
±1.0
40.0
V
µA
µA
V
V
IN
=
V
IH
or V
IL
I
OL
=
4 mA
I
OL
=
8 mA
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
I
OL
=
50
µA
V
V
V
IN
=
V
IH
or V
IL
I
OH
= −4
mA
I
OH
= −8
mA
I
OH
= −50 µA
Typ
Max
T
A
= −40°C
to
+85°C
Min
1.50
0.7 V
CC
0.50
0.3 V
CC
Max
Units
V
V
Conditions
Noise Characteristics
Symbol
V
OLP
(Note 3)
V
OLV
(Note 3)
V
IHD
(Note 3)
V
ILD
(Note 3)
Parameter
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
T
A
=
25°C
Typ
0.4
−0.4
Limits
0.8
−0.8
3.5
1.5
Units
V
V
V
V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Conditions
Note 3:
Parameter guaranteed by design.
www.fairchildsemi.com
4
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
