74AC11648DW datasheet, PDF - EEWORLD Datasheet

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74AC11648DW: DescriptionRegistered Bus Transceiver, AC Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO28, PLASTIC, SO-28; Categorylogic; File Size122KB，9 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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74AC11648DW Overview

Registered Bus Transceiver, AC Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO28, PLASTIC, SO-28

74AC11648DW Parametric

Parameter Name	Attribute value
Maker	Rochester Electronics
package instruction	SOP,
Reach Compliance Code	unknown
Other features	SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA
series	AC
JESD-30 code	R-PDSO-G28
length	17.9 mm
Logic integrated circuit type	REGISTERED BUS TRANSCEIVER
Number of digits	8
Number of functions	1
Number of ports	2
Number of terminals	28
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	INVERTED
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
propagation delay (tpd)	12.8 ns
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	7.5 mm
Base Number Matches	1

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74AC11648

OCTAL BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCAS114 – MARCH 1990 – REVISED APRIL 1993

•

Independent Registers for A and B Buses

Multiplexed Real-Time and Stored Data

Inverting Data Paths

Flow-Through Architecture Optimizes

PCB Layout

Center-Pin V

and GND Configurations

Minimize High-Speed Switching Noise

EPIC

™

(Enhanced-Performance Implanted

CMOS) 1-µm Process

500-mA Typical Latch-Up Immunity

at 125°C

Package Options Include Plastic

Small-Outline Packages and Standard

Plastic 300-mil DIPs

DW OR NT PACKAGE

(TOP VIEW)

description

GND

DIR

CLKAB

SAB

CLKBA

SBA

The 74AC11648 consists of bus transceiver

circuits, D-type flip-flops, and control circuitry

arranged for multiplexed transmission of data

directly from the input bus or from the internal

registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock

(CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be

performed with the 74AC11648.

Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the

transceiver mode, data present at the high-impedance port may be stored in either register or in both.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The

direction control (DIR) determines which bus will receive data when OE is low. In the isolation mode (OE high),

A data may be stored in one register and/or B data may be stored in the other register.

When an output function is disabled, the input function is still enabled and may be used to store and transmit

data. Only one of the two buses, A or B, may be driven at a time.

The 74AC11648 is characterized for operation from – 40°C to 85°C.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1993, Texas Instruments Incorporated

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

2–1

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