W83627DHG
WINBOND LPC I/O
Note: This document is for UBC, UBE and UBF version
except specified descriptions
Date : April 10, 2007
Version : 1.4
W83627DHG
Data Sheet Revision History
PAGES
DATES
VERSION
WEB
VERSION
MAIN CONTENTS
1
2
N.A.
N.A.
12/15/2005
02/22/2006
0.1
0.2
N.A.
N.A.
1.
1.
1.
2.
3.
4.
5.
6.
7.
1.
2.
3.
4.
First published version.
Add descriptions of the registers, functions,, AC/DC
timing, and top marking
Revise Table 8.1 and the timing chart of section 10.3.1
Add registers for AMDSI at LDB, CRF5h,CRF6h and
F7h(Bank1)
Swap LDB, CRF2h bit 0 and bit 1.
Modify the default values for LDA, CRFEh
Modify the descriptions of LD9, CR30h bit 0 and
CRF7h bit 4.
Remove LDA, CRE9h bit4 ~ 3
Swap LDC, CRE0h bit3~0 and CRE5h bit7~4
Add FDC, UART, Parallel Port and KBC interface
descriptions
Remove all the descriptions about AMDSI
Modify the diagrams and descriptions for Current Mode
Add two control bits for the selections of SYSFANOUT
and CPUFANOUT0 output type at CR[24h]
Remove the description of the internal pulled-up
resistor of Parallel Port
Modify the definitions of edge/level and enable/disable
debounce circuit of GP30, GP31 and GP35
Modify the descriptions of LD7, CRF7h and LD9,
CRE6h ~ CRE9h
Remove the remaining descriptions about AMDSI in
datasheet ver.0.4
Add a note for Index# of FDC Interface and pin
83(GP42) of Serial Port & Infrared Port Interface in Pin
Description
Reserve the bit 7 of LD0, CRF0h
Modify the descriptions of TRAK0#, WP#, RDATA#
and DSKCHG# of FDC Interface
Modify the descriptions for strapping pins: HEFRAS,
PENROM, PENKBC and EN_GTL
Modify the DC spec.
Remove the note and renew the descriptions for
Index# of FDC Interface.
Correct the descriptions of HM Device Bank 0, CR[12h]
bit0.
Add two control bits for AUXFANOUT and
CPUFAOUT1 output type selection.
Add a new bit at LDC, CR[E8h] bit 1 for more PECI
3
N.A.
03/15/2006
0.3
N.A.
4
N.A.
05/05/2006
0.4
N.A.
5.
6.
7.
8.
Correct typos and grammatical mistakes
5
N.A
05/15/2006
0.41
N.A
1.
1.
6
N.A.
05/19/2006
0.42
N.A
2.
3.
4.
5.
1.
2.
7
N.A.
06/23/2006
0.5
N.A.
3.
4.
-I-
Publication Release Date: Aug, 22, 2007
Version 1.4
W83627DHG
WEB
VERSION
PAGES
DATES
VERSION
MAIN CONTENTS
5.
1.
clock selection.
Modify the default values of HM Device Bank 0,
CR[43h] bit 5,0 and CR[46h] bit 2~1.
Add new chapters for Serial Peripheral Interface,
Configuration Register Access Protocol, Power
Management, Serialized IRQ, Watchdog Timer VID
Inputs and Outputs, and PCI Reset Buffers.
Update the feature lists of the W83627DHG in Chapter
2 Features.
Add descriptions of PECI and SST and a table of
SMBus in Chapter 5 Pin Description.
Add new sections of Caseopen and Beep Alarm
Function in Chapter 7 Hardware Monitor.
Add Clock Input Timing, PECI & SST Timing, and SPI
Timing in Chapter 21 Specifications.
Remove sections 9.4 and 9.5 (EXTFDD and
EXT2FDD).
Modify the descriptions of Hardware Monitor Device,
Bank 0, Index 59h, bits(6..4).
Add a beep control bit for VIN4 at Hardware Monitor
Device, Bank 0, Index 57h, bit6.
Remove status bit of PME# status of MIDI IRQ event at
Logical Device A, CRF4, bit 1.
Remove control bit of enable/disable PME# of MIDI at
Logical Device A, CRF7, bit 1.
Modify the descriptions of Tape Drive Register in
Chapter 10 Floppy Disk Controller.
Correct the description of Digital Input Register, bit
(6-4) in Chapter 10 Floppy Disk Controller.
Remove the description of “MR pin” in Digital Output
Register in Chapter 10 Floppy Disk Controller.
Adapt “Serial Flash Interface” to “Serial Peripheral
Interface”.
Modify “Absolute Maximum Ratings” in Chapter 21
Specifications.
Remove “V
DD
is 5V± 10% tolerance” from the
description of DC Characteristics in Chapter 21
Specifications.
2.
3.
4.
5.
6.
7.
8.
N.A.
09/29/2006
0.6
N.A.
9.
10.
11.
12.
13.
14.
15.
16.
8
17. Update “
S5
c o l d
state” to “S5 state.
18.
Remove the section of “AT Interface” in Chapter
10 Floppy Disk Controller.
9
N.A.
10/05/2006
1.0
N.A.
1.
1.
Update AC Timing parameters and waveforms.
Update Table 9.1 and Table 9.2 in Chapter 9 Serial
Peripheral Interface
Update CR2Ah in Chapter 20 Configuration Register
Modify CR24h bit 0 to reserved
10
N.A.
12/12/2006
1.1
N.A.
2.
3.
-II-
Publication Release Date: Aug, 22, 2007
Version 1.4
W83627DHG
WEB
VERSION
PAGES
DATES
VERSION
MAIN CONTENTS
4.
5.
Use “Tbase” instead of “TControl”
Add the pins, registers description and AC timing for
new ACPI function – VSBGATE#, ATXPGD,
FTPRST, PWROK2 and SUSC#
Modify the description for VSBGATE#, ATXPGD,
FTPRST.
Revise the definition for Logical Device A, CR[E5h]
bit 0.
Add new section of PWROK Generation in Chapter
14 Power Management Event.
Add new timing of VSBGATE# in Chapter 21
Specifications.
Modify the description of CR[2Ah], bits [7:4].
Modify the “t1” timing of RSMRST#.
Modify the descriptions of 7.7.2 OVT# Interrupt
Mode.
Modify the “t3” and “t4” timing in Table 14.4 and
section 21.3.3
Add a new DC spec. of RSMRST# PWROK for UBF
version (In section 14.3 and 14.4)
Add LPC Timing in section 21.4
Remove redundant Power on/off and LRESET#
Timing
Modify LPC Timing in section 21.4
1.
2.
3.
11
N.A.
01/25/2007
1.2
N.A.
4.
5.
6.
7.
8.
1.
12
N.A.
03/28/2007
1.3
N.A.
2.
3.
1.
13
N.A.
04/10/2007
1.4
N.A.
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Winbond for any damages resulting from such improper use or sales.
-III-
Publication Release Date: Aug, 22, 2007
Version 1.4
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