AM29BDS643DT9AWLI datasheet, PDF

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AM29BDS643DT9AWLI: Description64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory; Categorystorage storage; File Size398KB，46 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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AM29BDS643DT9AWLI Overview

64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

AM29BDS643DT9AWLI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	TFBGA, BGA48,8X14,40/20
Contacts	48
Reach Compliance Code	unknow
ECCN code	3A991.B.1.A
Maximum access time	20 ns
Other features	CAN ALSO OPERATE IN ASYNCHRONOUS MODE
startup block	TOP
command user interface	YES
Data polling	YES
JESD-30 code	R-PBGA-B48
JESD-609 code	e0
length	11 mm
memory density	67108864 bi
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	8,127
Number of terminals	48
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA48,8X14,40/20
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
power supply	1.8 V
Programming voltage	1.8 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1.2 mm
Department size	4K,32K
Maximum standby current	0.00001 A
Maximum slew rate	0.06 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
switch bit	YES
type	NOR TYPE
width	10 mm
Base Number Matches	1

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PRELIMINARY

Am29BDS643D

64 Megabit (4 M x 16-Bit)

CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

DISTINCTIVE CHARACTERISTICS

Single 1.8 volt read, program and erase (1.7 to

1.9 volt)

Multiplexed Data and Address for reduced I/O

count

— A0–A15 multiplexed as D0–D15

— Addresses are latched with AVD# control inputs

while CE# low

Simultaneous Read/Write operation

— Data can be continuously read from one bank

while executing erase/program functions in other

bank

— Zero latency between read and write operations

Read access times at 54 MHz/40 MHz

— Burst access times of 13.5/20 ns @ 30 pF

at industrial temperature range

— Asynchronous random access times

of 90/90 ns @ 30 pF

— Synchronous random access times

of 106/120 ns @ 30 pF

Burst length

— Continuous linear burst

Power dissipation (typical values, 8 bits

switching, C

= 30 pF)

— Burst Mode Read: 25 mA

— Simultaneous Operation: 40 mA

— Program/Erase: 15 mA

— Standby mode: 0.2 µA

Sector Architecture

— Eight 4 Kword sectors and one hundred

twenty-seven 32 Kword sectors

— Bank A contains the eight 4 Kword sectors and

thirty-one 32 Kword sectors

— Bank B contains ninety-six 32 Kword sectors

Sector Protection

— Software command sector locking

— WP# protects the last two boot sectors

— All sectors locked when V

= V

Handshaking feature

— Provides host system with minimum possible

latency by monitoring RDY

Software command set compatible with JEDEC

42.4 standards

— Backwards compatible with Am29F and Am29LV

families

Minimum 1 million erase cycle guarantee

per sector

20-year data retention at 125°C

— Reliable operation for the life of the system

Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

Data# Polling and toggle bits

— Provides a software method of detecting

program and erase operation completion

Erase Suspend/Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

Hardware reset input (RESET#)

— Hardware method to reset the device for reading

array data

CMOS compatible inputs, CMOS compatible

outputs

Low V

write inhibit

48-Ball FBGA package

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication#

23709

Rev:

Amendment/+3

Issue Date:

December 21, 2000

Refer to AMD’s Website (www.amd.com) for the latest information.

P R E L I M I N A R Y

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram of

Simultaneous Operation Circuit . . . . . . . . . . . . . . 5

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6

Special Handling Instructions for FBGA Package .................... 6

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Device Bus Operations ......................................................9

Figure 3. Data# Polling Algorithm .................................................. 23

DQ6: Toggle Bit I .................................................................... 24

Figure 4. Toggle Bit Algorithm........................................................ 24

DQ2: Toggle Bit II ................................................................... 25

Table 5. DQ6 and DQ2 Indications ................................................ 25

Reading Toggle Bits DQ6/DQ2 ............................................... 25

DQ5: Exceeded Timing Limits ................................................ 25

DQ3: Sector Erase Timer ....................................................... 26

Table 6. Write Operation Status ..................................................... 26

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 27

Figure 5. Maximum Negative Overshoot Waveform ...................... 27

Figure 6. Maximum Positive Overshoot Waveform........................ 27

Requirements for Asynchronous Read Operation (Non-Burst) 9

Requirements for Synchronous (Burst) Read Operation .......... 9

Programmable Wait State ...................................................... 10

Handshaking ........................................................................... 10

Power Saving Function ........................................................... 10

Simultaneous Read/Write Operations with Zero Latency ....... 10

Writing Commands/Command Sequences ............................ 10

Accelerated Program Operation ............................................. 11

Autoselect Functions .............................................................. 11

Automatic Sleep Mode ........................................................... 11

RESET#: Hardware Reset Input ............................................. 11

Output Disable Mode .............................................................. 11

Hardware Data Protection ...................................................... 12

Low VCC Write Inhibit ............................................................ 12

Write Pulse “Glitch” Protection ............................................... 12

Logical Inhibit .......................................................................... 12

Table 2. Sector Address Table ........................................................13

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 27

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 7. Test Setup....................................................................... 29

Table 7. Test Specifications ........................................................... 29

Key to Switching Waveforms. . . . . . . . . . . . . . . . 29

Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . 29

Figure 8. Input Waveforms and Measurement Levels ................... 29

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30

Synchronous/Burst Read ........................................................ 30

Figure 9. Burst Mode Read (54 MHz) ............................................ 30

Figure 10. Burst Mode Read (40 MHz) .......................................... 31

Asynchronous Read ............................................................... 32

Figure 11. Asynchronous Mode Read............................................ 32

Figure 12. Reset Timings............................................................... 33

Erase/Program Operations ..................................................... 34

Figure 13. Program Operation Timings..........................................

Figure 14. Chip/Sector Erase Operations ......................................

Figure 15. Accelerated Unlock Bypass Programming Timing........

Figure 16. Data# Polling Timings (During Embedded Algorithm) ..

Figure 17. Toggle Bit Timings (During Embedded Algorithm)........

Figure 18. Latency with Boundary Crossing ..................................

Figure 19. Initial Access with Power Saving (PS)

Function and Address Boundary Latency ......................................

Figure 20. Example of Five Wait States Insertion

(Non-Handshaking Device) ............................................................

Figure 21. Back-to-Back Read/Write Cycle Timings ......................

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 17

Reading Array Data ................................................................ 17

Set Wait State Command Sequence ...................................... 17

Table 3. Third Cycle Address/Data .................................................17

Handshaking ........................................................................... 17

Enable PS (Power Saving) Mode Command Sequence ........ 17

Sector Lock/Unlock Command Sequence .............................. 17

Reset Command ..................................................................... 18

Autoselect Command Sequence ............................................ 18

Program Command Sequence ............................................... 18

Unlock Bypass Command Sequence ..................................... 18

Figure 1. Program Operation .......................................................... 19

Chip Erase Command Sequence ........................................... 19

Sector Erase Command Sequence ........................................ 20

Erase Suspend/Erase Resume Commands ........................... 20

Figure 2. Erase Operation............................................................... 21

Command Definitions ............................................................. 22

Table 4. Command Definitions .......................................................22

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 23

DQ7: Data# Polling ................................................................. 23

Erase and Programming Performance . . . . . . . 43

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 44

FDE048—48-Pin Fine-Pitch Ball Grid Array (FBGA)

11 x 10 mm package ............................................................. 44

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46

Revision A (June 20, 2000) .................................................... 46

Revision A+1 (November 27, 2000) ....................................... 46

Revision A+2 (November 30, 2000) ....................................... 46

Revision A+3 (December 21, 2000) ....................................... 46

Am29BDS643D

AM29BDS643DT9AWLI Related Products

	AM29BDS643DT9AWLI	AM29BDS643D	AM29BDS643DT9BWLI
Description	64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory	64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory	64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
package instruction	TFBGA, BGA48,8X14,40/20	,	TFBGA, BGA48,8X14,40/20
Reach Compliance Code	unknow	unknow	unknow
Base Number Matches	1	1	1
Is it Rohs certified?	incompatible	-	incompatible
Parts packaging code	BGA	-	BGA
Contacts	48	-	48
ECCN code	3A991.B.1.A	-	3A991.B.1.A
Maximum access time	20 ns	-	13.5 ns
Other features	CAN ALSO OPERATE IN ASYNCHRONOUS MODE	-	CAN ALSO OPERATE IN ASYNCHRONOUS MODE
startup block	TOP	-	TOP
command user interface	YES	-	YES
Data polling	YES	-	YES
JESD-30 code	R-PBGA-B48	-	R-PBGA-B48
JESD-609 code	e0	-	e0
length	11 mm	-	11 mm
memory density	67108864 bi	-	67108864 bi
Memory IC Type	FLASH	-	FLASH
memory width	16	-	16
Number of functions	1	-	1
Number of departments/size	8,127	-	8,127
Number of terminals	48	-	48
word count	4194304 words	-	4194304 words
character code	4000000	-	4000000
Operating mode	SYNCHRONOUS	-	SYNCHRONOUS
Maximum operating temperature	85 °C	-	85 °C
Minimum operating temperature	-40 °C	-	-40 °C
organize	4MX16	-	4MX16
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	TFBGA	-	TFBGA
Encapsulate equivalent code	BGA48,8X14,40/20	-	BGA48,8X14,40/20
Package shape	RECTANGULAR	-	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	-	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	-	PARALLEL
power supply	1.8 V	-	1.8 V
Programming voltage	1.8 V	-	1.8 V
Certification status	Not Qualified	-	Not Qualified
ready/busy	YES	-	YES
Maximum seat height	1.2 mm	-	1.2 mm
Department size	4K,32K	-	4K,32K
Maximum standby current	0.00001 A	-	0.00001 A
Maximum slew rate	0.06 mA	-	0.06 mA
Maximum supply voltage (Vsup)	1.9 V	-	1.9 V
Minimum supply voltage (Vsup)	1.7 V	-	1.7 V
Nominal supply voltage (Vsup)	1.8 V	-	1.8 V
surface mount	YES	-	YES
technology	CMOS	-	CMOS
Temperature level	INDUSTRIAL	-	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)
Terminal form	BALL	-	BALL
Terminal pitch	0.5 mm	-	0.5 mm
Terminal location	BOTTOM	-	BOTTOM
switch bit	YES	-	YES
type	NOR TYPE	-	NOR TYPE
width	10 mm	-	10 mm

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