EEWORLDEEWORLDEEWORLD

Part Number

Search

530WC1305M00DGR

Description
CMOS/TTL Output Clock Oscillator, 1305MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
Categoryoscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

530WC1305M00DGR Overview

CMOS/TTL Output Clock Oscillator, 1305MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530WC1305M00DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability7%
JESD-609 codee4
Manufacturer's serial number530
Installation featuresSURFACE MOUNT
Nominal operating frequency1305 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS/TTL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
How to download the bootloader and user program at the same time?
How much FLASH space do you reserve for the bootloader?...
cxy752528 stm32/stm8
Analysis of the front-end circuit of push-pull amplifier
See the picture. This is the front end of the push-pull amplifier. Points a and b are connected to the next level. Please solve the voltage of a and b. If the AC signal is a small signal, it can be an...
wh40062 Analog electronics
Why does Workbench3.0 show "failed to connect to the wind river registry on host" every time it starts?
And there is a red cross on the default (localhost) in the lower left corner. Tornado has been uninstalled but it still doesn't work. There is no Tornado registry in the service. Every time I start it...
cdqd Embedded System
Actel to begin shipping FPGA samples with mixed analog circuits and flash memory
[;)][;)][;)]  Actel Inc. of the United States recently announced the first four products of its FPGA series "Fusion" that mixes analog circuits and flash memory, and will start shipping samples of one...
fighting Analog electronics
How to change the component package in PCB?
Experts, the capacitor package in the picture is a bit big, how can I change it to a smaller package? Thank you very much...
huohuiqing PCB Design
Addressing, how to get the value in external ROM through RO/R1
The sample code is as follows: ORG 0000H LJMP MAIN ORG 0100H MAIN: MOV 50H,#16H; Set RAM, data at position 0x50 MOV 51H,#17H MOV R0,#50H; Set the starting position of indirect addressing MOV A,@R0; Ge...
xrg0228 Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1675  1254  2098  49  2564  34  26  43  1  52 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号