EEWORLDEEWORLDEEWORLD

Part Number

Search

530FA985M000DGR

Description
LVDS Output Clock Oscillator, 985MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
Categoryoscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

530FA985M000DGR Overview

LVDS Output Clock Oscillator, 985MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530FA985M000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Manufacturer's serial number530
Installation featuresSURFACE MOUNT
Nominal operating frequency985 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVDS
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Bike modification series: button
[i=s]This post was last edited by dcexpert on 2021-10-13 12:56[/i]To control, you need to choose the right button. There are two general types of buttons: self-locking and reset. Self-locking buttons ...
dcexpert Energy Infrastructure?
Introduction to cache operation interface of Allwinner V85 development board RTOS platform
## 1. TopicIntroduction to cache operation interface of Allwinner F series/R series/V series RTOS platform ## 2. Problem BackgroundThe RTOS used by Allwinner F series/R series/V series provides some c...
aleksib Domestic Chip Exchange
How to use Type C for power sharing? Here are three ways
Method 1 [align=left][font=微软雅黑][color=#0000ff][size=16px]An obvious way to share power is to limit the power of each port, ensuring that the total power output does not exceed the input power. But in...
maylove Analogue and Mixed Signal
Beginner's Guide to FPGA (4) Incomplete Conditional Statements and Sequential Circuits (EEFPGA Learning Plan)
… BEGIN IF CLK'EVENT AND CLK='1'THEN Q1=D; END IF; Incomplete conditional statements: In a conditional statement, there is no corresponding way to handle all possible situations. For this phenomenon, ...
zl_felix FPGA/CPLD
Welcome fengzhang2002 and ddllxxrr to become the moderators of the "E-shopping Experience" section
:victory:Other friends who love Taobao are looking forward to your joining~~...
soso Buy&Sell
Software and Hardware Design of Embedded GSM Short Message Interface
[b]Introduction[/b] SMS (Short Message Service) is an application service provided by the GSM (Global System for Mobile Communication) system for sending and receiving text messages between GSM termin...
songbo Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2248  1522  2142  1125  2377  46  31  44  23  48 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号