531DB1130M00DGR datasheet, PDF

Datasheet> All Categories > oscillator> 531DB1130M00DGR

531DB1130M00DGR: DescriptionCMOS/TTL Output Clock Oscillator, 1130MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; Categoryoscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531DB1130M00DGR Overview

CMOS/TTL Output Clock Oscillator, 1130MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531DB1130M00DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	1130 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Photocell amplification control circuit

range hood circuit

79 series basic application circuit

Second-order low-pass active filter circuit with gain of 1

Single Tube TV Antenna Amplifier 2

Automatic gain control amplifier circuit

LM3s8962 Experience 6... Clock Register Operation: Clock Settings 1. IntroductionThis program experiment uses the change register to set the system clock to change. The software delay changes due to the system clock. Further changes the beeping time i...; sdjntl Microcontroller MCU

Domestic automotive battery industry faces both opportunities and challenges: The rapid development of my country's automobile industry has brought unprecedented opportunities to the battery industry. In the past 10 years, the average growth rate of total battery production has...; 1ying Automotive Electronics

Small show prizes: The courier called me early in the morning. I was wondering why I hadn't bought anything recently. Then I was relieved. It must be a prize from EE. I went downstairs and got it. It looks very beautifu...; Bingqi23 Talking

About Xilinx DCM: There is an option "Wait for DLL Lock" in ISE , the purpose of which is to set whether the FPGA waits for the "lock" signal of the DCM.The default setting is nowait. I want to set it to standby mode, ...; qd0090 FPGA/CPLD

[Help] How to use AVR Studio4 to simulate C language: How can I use AVR Studio4 to simulate C language? I wrote a C language program with Winavr and compiled it successfully to generate a file with the suffix cof. When I opened the file with the suffix c...; STARKINGS Microchip MCU

Help: How to let a long-running function give up CPU time without using OS: It's like this, I have to erase the FLASH sectors multiple times in one function, it takes 2-3S to erase a sector, and after erasing the sector, the function has to complete other logics.I want to use...; amduron stm32/stm8

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components