September 2007
HYB18H512321BF–11/12/14
HYB18H512321BF–08/10
512-Mbit GDDR3 Graphics RAM
GDDR3 Graphics RAM
RoHS compliant
Internet Data Sheet
Rev. 1.1
Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
HYB18H512321BF–11/12/14
HYB18H512321BF–08/10
Revision History: 2007-09, Rev. 1.1
Page
34
34
Subjects (major changes since last revision)
Table 41 max. CL changed from 16 to 13
Table 41 - Timing Parameters for -8 updated
Previous Revision: Rev. 1.0, 2007-05
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Your feedback will help us to continuously improve the quality of this document.
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qag_techdoc_rev411 / 3.31 QAG / 2007-01-22
05292007-WAU2-UU95
2
Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
1
1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Overview
Features
• Data mask for write commands
• Single ended READ strobe (RDQS) per byte. RDQS edge-
aligned with READ data
• Single ended WRITE strobe (WDQS) per byte. WDQS
center-aligned with WRITE data
• DLL aligns RDQS and DQ transitions with Clock
• Programmable IO interface including on chip termination
(ODT)
• Autoprecharge option with concurrent auto precharge
support
• 8k Refresh (32ms)
• Autorefresh and Self Refresh
• PG–TFBGA–136 package (10mm
×
14mm)
• Calibrated output drive. Active termination support
• RoHS Compliant Product
1)
This chapter lists all main features of the product family HYB18H512321BF and the ordering information.
2.0 V
V
DDQ
IO voltage HYB18H512321BF–08/10
2.0 V
V
DD
core voltage HYB18H512321BF–08/10
1.8 V
V
DDQ
IO voltage HYB18H512321BF–11/12/14
1.8 V
V
DD
core voltage HYB18H512321BF–11/12/14
Organization: 2048K
×
32
×
8 banks
4096 rows and 512 columns (128 burst start locations) per
bank
Differential clock inputs (CLK and CLK)
CAS latencies of 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17
Write latencies of 3, 4, 5, 6, 7
Burst sequence with length of 4, 8.
4n pre fetch
Short RAS to CAS timing for Writes
t
RAS
Lockout support
t
WR
programmable for Writes with Auto-Precharge
TABLE 1
Ordering Information
Part Number
1)
HYB18H512321BF–11/12/14
HYB18H512321BF–08/10
1) HYB: designator for memory components
18H:
V
DDQ
= 1.8 V
512: 512-Mbit density
32: Organization
B: Product revision
F: Lead- and Halogen-Free
Organisation
×32
Clock (MHz)
1200/1000/900/800/700
Package
PG–TFBGA–136
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.1, 2007-09
05292007-WAU2-UU95
3
Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
1.2
Description
The Qimonda 512-Mbit GDDR3 Graphics RAM is a high speed memory device, designed for high bandwidth intensive
applications like PC graphics systems. The chip’s 8 bank architecture is optimized for high speed.
HYB18H512321BF uses a double data rate interface and a 4
n
-pre fetch architecture. The GDDR3 interface transfers two 32
bit wide data words per clock cycle to/from the I/O pins. Corresponding to the 4
n
-pre fetch a single write or read access consists
of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, one-half-clock-
cycle data transfers at the I/O pins.
Single-ended unidirectional Read and Write Data strobes are transmitted simultaneously with Read and Write data respectively
in order to capture data properly at the receivers of both the Graphics SDRAM and the controller. Data strobes are organized
per byte of the 32 bit wide interface. For read commands the RDQS are edge-aligned with data, and the WDQS are center-
aligned with data for write commands.
The HYB18H512321BF operates from a differential clock (CLK and CLK). Commands (addresses and control signals) are
registered at every positive edge of CLK. Input data is registered on both edges of WDQS, and output data is referenced to
both edges of RDQS.
In this document references to “the positive edge of CLK” imply the crossing of the positive edge of CLK and the negative edge
of CLK. Similarly, the “negative edge of CLK” refers to the crossing of the negative edge of CLK and the positive edge of CLK.
References to RDQS are to be interpreted as any or all RDQS<3:0>. WDQS, DM and DQ should be interpreted in a similar
fashion.
Read and write accesses to the HYB18H512321BF are burst oriented. The burst length is fixed to 4 and 8 and the two least
significant bits of the burst address are “Don’t Care” and internally set to LOW. Accesses begin with the registration of an
ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVATE command are used to select the bank and the row to be accessed. The address bits registered coincident with the
READ or WRITE command are used to select the bank and the column location for the burst access. Each of the 8 banks
consists of 4096 row locations and 512 column locations. An AUTO PRECHARGE function can be combined with READ and
WRITE to provide a self-timed row precharge that is initiated at the end of the burst access. The pipe lined, multibank
architecture of the HYB18H512321BF allows for concurrent operation, thereby providing high effective bandwidth by hiding row
precharge and activation time.
The “On Die Termination” interface (ODT) is optimized for high frequency digital data transfers and is internally controlled. The
termination resistor value can be set using an external ZQ resistor or disabled through the Extended Mode Register.
The output driver impedance can be set using the Extended Mode Register. It can either be set to ZQ / 6 (auto calibration) or
to 35, 40 or 45 Ohms.
Auto Refresh and Power Down with Self Refresh operations are supported.
An industrial standard PG–TFBGA–136 package is used which enables ultra high speed data transfer rates and a simple
upgrade path from former DDR Graphics SDRAM products.
Rev. 1.1, 2007-09
05292007-WAU2-UU95
4
Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
2
Configuration
FIGURE 1
Ballout 512-Mbit GDDR3 Graphics RAM [Top View, MF = Low ]
1
2
3
4
ZQ
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
V
7
8
9
MF
10
11
12
V
DDQ
V
SSQ
V
DDQ
V
DD
DQ0
DQ2
V
SS
DQ1
DQ3
V
SS
DQ9
DQ11
V
DD
DQ8
DQ10
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
DD
V
SS
V
REF
V
SS
V
DD
V
SS
V
DD
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DDQ
CAS
BA0
CKE
V
SSQ
V
DDQ
V
SSQ
V
DDQ
CS
BA1
WE
V
SSQ
WDQS0 RDQS0
V
DDQ
V
DD
V
SS
V
REF
V
SS
V
DD
V
SS
V
DD
V
DDQ
DQ4
DQ6
DM0
DQ5
DQ7
RAS
RFU
A2
DQ25
DQ27
DM3
RDQS1 WDQS1
DM1
DQ13
DQ15
BA2
CK
A6
DQ17
DQ19
DM2
DQ12
DQ14
V
SSQ
A1
RFU
A10
V
SSQ
A5
CK
A8/AP
V
DDQ
A0
A11
A3
V
DDQ
A4
A7
A9
V
SSQ
DQ24
DQ26
V
SSQ
DQ16
DQ18
V
DDQ
V
SSQ
V
DDQ
V
SSQ
SEN
V
DDQ
V
SSQ
V
DDQ
V
SSQ
RESET
V
SSQ
WDQS3 RDQS3
V
DDQ
V
SSQ
V
DDQ
DQ28
DQ30
DQ29
DQ31
RDQS2 WDQS2
DQ21
DQ23
DQ20
DQ22
V
DD
V
SS
V
SS
V
DD
Rev. 1.1, 2007-09
05292007-WAU2-UU95
5
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