ML145406
Driver/Receiver
EIA 232–E and CCITT V.28
(Formerly RS–232–D)
Legacy Device:
Motorola MC145406
The ML145406 is a silicon–gate CMOS IC that combines three drivers and
three receivers to fulfill the electrical specifications of standards EIA 232–E
and CCITT V The drivers feature true TTL input compatibility,
.28.
slew–rate–limited output, 300–Ω power–off source impedance, and output typ-
ically switching to within 25% of the supply rails. The receivers can handle up
to ±25 V while presenting 3 to 7 kΩ impedance. Hysteresis in the receivers
aids reception of noisy signals. By combining both drivers and receivers in a
single CMOS chip, the ML145406 provides efficient, low–power solutions for
EIA 232–E and V applications.
.28
This device offers the following performance features:
• Operating Temperature Range = TA –40° to +85°C
Drivers
• ± 5 V to ±12 V Supply Range
• 300–Ω Power–Off Source Impedance
• Output Current Limiting
• TTL Compatible
• Maximum Slew Rate = 30 V/µs
Receivers
• ± 25 V Input Voltage Range When VDD = 12 V VSS = – 12 V
,
• 3 to 7 kΩ Input Impedance
• Hysteresis on Input Switchpoint
BLOCK DIAGRAM
VDD
RECEIVER
VDD
VCC
15 k
+
–
VSS
1.0 V
Rx2
1.8 V
HYSTERESIS
VDD
Rx3
DRIVER
VCC
300
Tx
LEVEL
SHIFT
+
–
1.4 V
DI
Tx3
VSS
7
D
10
DI3
GND
6
R
11
DO3
Tx2
DO
VCC
VDD
Rx1
Tx1
1
2
3
4
5
R
D
R
D
16
15
14
13
12
VCC
DO1
DI1
DO2
DI2
P DIP 16 = EP
PLASTIC
CASE 648
16
1
16
1
SO 16W = -5P
SOG
CASE 751G
CROSS REFERENCE/ORDERING INFORMATION
LANSDALE
PACKAGE
MOTOROLA
P DIP 16
SO 16W
MC145406P
MC145406DW
ML145406EP
ML145406-6P
Note:
Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from
ML
to
MLE.
PIN ASSIGNMENT
*
Rx
5.4 k
8
9
D = DRIVER
R = RECEIVER
VSS
*Protection circuit
Page 1 of 10
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ML145406
LANSDALE Semiconductor, Inc.
MAXIMUM RATINGS
(Voltage polarities referenced to GND)
Rating
DC Supply Voltages (VDD
≥
VCC)
Symbol
VDD
VSS
VCC
VIR
(VSS – 15) to (VDD + 15)
– 0.5 to (VCC + 0.5)
±
100
PD
TA
Tstg
1.0
– 40 to + 85
– 85 to + 150
mA
W
°C
°C
Value
– 0.5 to + 13.5
+ 0.5 to – 13.5
– 0.5 to + 6.0
Unit
V
This device contains protection circuitry to pro-
tect the inputs against damage due to high static
voltages or electric fields; however, it is advised
that normal precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
voltages to this high impedance circuit. For proper
operation, it is recommended that the voltages at
the DI and DO pins be constrained to the range
GND
≤V
DI
≤
VCC and GND≤ VDO
≤
VCC. Also, the
voltage at the Rx pin should be constrained to
(VSS – 15 V)
≤
VRx1–3
≤
(VDD + 15 V), and Tx
should be constrained to VSS
≤
VTx1–3
≤
VDD.
Unused inputs must always be tied to an ap-
propriate logic voltage level (e.g., GND or VCC for
DI and Ground for Rx.)
Input Voltage Range
Rx1–3 Inputs
DI1–3 Inputs
DC Current Per Pin
Power Dissipation
Operating Temperature Range
Storage Temperature Rate
V
DC ELECTRICAL CHARACTERISTICS
(All polarities referenced to GND = 0 V, TA = – 40 to + 85°C)
Parameter
DC Supply Voltage
VDD
VSS
VCC (VDD
≥
VCC)
Quiescent Supply Current (Outputs unloaded, inputs low)
VDD = + 12 V
VSS = – 12 V
VCC = + 5 V
Symbol
VDD
VSS
VCC
IDD
ISS
ICC
Min
4.5
– 4.5
4.5
—
—
—
Typ
5 to 12
– 5 to – 12
5.0
140
340
300
Max
13.2
– 13.2
5.5
µA
400
600
450
Unit
V
RECEIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GND = 0 V, VDD = + 5 to + 12 V, VSS = – 5 to – 12 V, VDD
≥
VCC, TA = – 40 to + 85°C)
Characteristic
Input Turn–on Threshold
VDO1–DO3 = VOL, VCC = 5.0 V
±
5%
Input Turn–off Threshold
VDO1–DO3 = VOH, VCC = 5.0 V
±
5%
Input Threshold Hysteresis
VCC = 5.0 V
±
5%
Input Resistance
(VSS – 15 V)
≤
VRx1–Rx3
≤
(VDD + 15 V)
High–Level Output Voltage (VRx1–Rx3 = – 3 V to (VSS – 15 V))*
DO1–DO3
IOH = – 20
µA,
VCC = + 5.0 V
IOH = – 1 mA, VCC = + 5.0 V
Low–Level Output Voltage (VRx1–Rx3 = + 3 V to (VDD + 15 V))* DO1–DO3
IOL = + 20
µA,
VCC = + 5.0 V
IOL = + 2 mA, VCC = + 5.0 V
IOL = + 4 mA, VCC = + 5.0 V
VOL
—
—
—
0.01
0.02
0.5
0.1
0.5
0.7
Rx1–Rx3
Rx1–Rx3
Rx1–Rx3
Rx1–Rx3
Symbol
Von
Voff
Von–Voff
Rin
VOH
4.9
3.8
4.9
4.3
—
—
V
Min
1.35
0.75
0.6
3.0
Typ
1.80
1.00
0.8
5.4
Max
2.35
1.25
—
7.0
Unit
V
V
V
k
V
* This is the range of input voltages as specified by EIA 232–E to cause a receiver to be in the high or low logic state.
Page 2 of 10
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ML145406
LANSDALE Semiconductor, Inc.
ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GND = 0 V, VCC = + 5 V
±
5%, TA = – 40 to + 85°C)
Characteristic
Digital Input Voltage
Logic 0
Logic 1
Input Current
VDI1–DI3 = VCC
DI1–DI3
VIL
VIH
DI1–DI3
Iin
VOH
3.5
4.3
9.2
VOL
– 4.0
– 4.5
– 10.0
300
ISC
—
—
– 4.3
– 5.2
– 10.3
—
—
—
—
—
mA
±
22
±
60
±
60
±
100
3.9
4.7
9.5
—
—
—
V
—
2.0
—
—
—
—
0.8
—
±
1.0
µA
V
Symbol
Min
Typ
Max
Unit
V
Output High Voltage (VDI1–3 = Logic 0, RL = 3.0 k )
Tx1–Tx3
VDD = + 5.0 V, VSS = – 5.0 V
VDD = + 6.0 V, VSS = – 6.0
VDD = + 12.0 V, VSS = – 12.0 V
Output Low Voltage* (VDI1–3 = Logic 1, RL = 3.0 k )
Tx1–Tx3
VDD = + 5.0 V, VSS = – 5.0 V
VDD = + 6.0 V, VSS = – 6.0 V
VDD = + 12.0 V, VSS = – 12.0 V
Off Source Resistance (Figure 1)
VDD = VSS = GND = 0 V, VTx1–Tx3 =
±
2.0 V
Tx1–Tx3
Output Short–Circuit Current (VDD = + 12.0 V, VSS = – 12.0 V)
Tx1–Tx3
Tx1–Tx3 shorted to GND**
Tx1–Tx3 shorted to
±
15.0 V***
* The voltage specifications are in terms of absolute values.
** Specification is for one Tx output pin to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power dissipation
limits will be exceeded.
*** This condition could exceed package limitations.
SWITCHING CHARACTERISTICS
(VCC = + 5 V
±
5%, TA = – 40 to + 85°C
Drivers
Characteristic
Propagation Delay Time
Low–to–High
High–to–Low
RL = 3 k
CL = 50 pF
SR
—
±
9
±
30
Output Slew Rate
Tx1–Tx3
Minimum Load
RL = 7 k , CL = 0 pF, VDD = + 6 to + 12 V, VSS = – 6 to – 12 V
Maximum Load
RL = 3 k , CL = 2500 pF
VDD = + 12 V, VSS = – 12 V
VDD = + 5 V, VSS = – 5 V
4
—
—
—
—
—
Tx1–Tx3
RL = 3 k , CL = 50 pF
tPLH
tPHL
—
300
500
V/µs
—
300
500
Symbol
Min
Typ
Max
Unit
ns
Receivers
(CL = 50 pF)
Characteristic
Propagation Delay Time
Low–to–High
High–to–Low
Output Rise Time
Output Fall Time
DO1–DO3
DO1–DO3
DO1–DO3
tPLH
tPHL
tr
tf
—
—
—
—
150
150
250
40
425
425
400
100
ns
ns
Symbol
Min
Typ
Max
Unit
ns
Page 3 of 10
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ML145406
LANSDALE Semiconductor, Inc.
1
VDD
14
DI1
16
VCC
Tx1
3
PIN
DESCRIPTIONS
VDD
Positive Power
Supply (Pin 1)
The most positive power supply pin, which is typically + 5
to +12V.
Vin =
±
2 V
12 DI2
Tx2 5
10
DI3
Tx3
7
VSS
Negative
Power
Supply (Pin 8)
The most negative power supply pin, which is typically – 5
to –12 V.
VSS GND
8
9
Vin
Rout =
I
VCC
Digital
Power
Supply (Pin 16)
The digital supply pin, which is connected to the logic power sup
ply (maximum +5.5 V). VCC
must
be less than or equal to VDD.
Figure 1. Power–Off Source Resistance (Drivers)
GND
Ground (Pin 9)
Ground return pin is typically connected to the signal groun
pin of the EIA 232–E connector (Pin 7) as well as to the logic
power supply ground.
DRIVERS
3V
DI1–DI3
50%
0V
tf
Tx1–Tx3
tPHL
90%
10%
tPLH
tr
VOH
VOL
RECEIVERS
+3V
Rx1–Rx3
50%
0V
tPHL
90%
DO1–DO3
50%
10%
tf
tr
tPLH
VOH
VOL
Rx1, Rx2, Rx3
Receive Data Input (Pins 2, 4, 6)
These are the EIA 232–E receive signal inputs whose volt-
ages can range from (VDD + 15 V) to (VSS – 15 V). A volt-
age between +3 and (VDD + 15 V) is decoded as a space and
causes the corresponding DO pin to swing to ground (0V); a
voltage between – 3 and (VDD – 15 V) is decoded as a mark
and causes the DO pin to swing up to VCC. The actual turn–o
input switch point is typically biased at 1.8 V above ground,
and includes 800mV of hysteresis for noise rejection. The
nominal input impedance is 5 kΩ. An open or grounded input
pin is interpreted as a mark, forcing the DO pin to VCC.
DO1, DO2, DO3
Data Output (Pins 11, 13, 15)
These are the receiver digital output pins, which swing from
VCC to GND. A space on the Rx pin causes DO to produce a
logic 0; a mark produces a logic 1. Each output pin is capable
of driving one LSTTL input load.
Figure 2. Switching Characteristics
DI1, DI2, DI3
Data Input (Pins 10, 12,14)
These are the high–impedance digital input pins to the driv-
ers. TTL compatibility is accomplished by biasing the input
switchpoint at 1.4 V above GND. However, 5V CMOS compat
ibility is maintained as well. Input voltage levels on these pins
must be between VCC and GND.
DRIVERS
Tx1–Tx3
tSLH
SLEW RATE (SR) =
3V
–3V
3V
–3V
tSHL
– 3 V – (3 V)
3 V – ( – 3 V)
OR
tSLH
tSHL
Figure 3. Slew–Rate Characterization
Tx1, Tx2, Tx3
Transmit Data Output(Pins 3, 5, 7)
These are the EIA 232–E transmit signal output pins, which
swing toward VDD and VSS. A logic 1 at a DI input causes th
corresponding Tx output to swing toward VSS. A logic 0 caus-
es the output to swing toward VDD (the output voltages will b
slightly less than VDD or VSS depending upon the output
load). Output slew rates are limited to a maximum of 30 V per
µs. When the ML145406 is off (VDD = VSS = VCC= GND),
the minimum output impedance is 300
Ω.
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Page 4 of 10
ML145406
LANSDALE Semiconductor, Inc.
Legacy Applications Information
The ML145406 has been designed to meet the electrical-
specifications of standards EIA 232–E and CCITT V.28. EIA
232–E defines the electrical and physical interface between
Data Communication Equipment (DCE) and DataTerminal
Equipment (DTE). A DCE is connected to a DTE using a cable
that typically carries up to 25 leads. These leads, referred to as
interchange circuits, allow the transfer of timing, data, control,
and test signals. Electrically this transfer requires level shifting
between the TTL/CMOS logic levels of the computer or
modem and the high voltage levels of EIA 232–E, which can
range from ±3 to ±25 V The ML145406 provides the neces-
.
sary level shifting as well as meeting other aspects of the EIA
232–E specification.
DRIVERS
As defined by the specification, an EIA 232–E driver pres-
ents a voltage of between ±5 to ±15 V into a load of between 3
to 7 kΩ. A logic 1 at the driver input results in a voltage of
between –5 to – 15 V. A logic 0 results in a voltage between +
5 to + 15V. When operating VDD and VSS at ±7 to ±12 V, the
ML145406 meets this requirement. When operating at ±5 V,
the ML145406 drivers produce less than ±5 V at the output
(when terminated), which does not meet EIA 232–E specifica-
tion. However, the output voltages when using a ±5 V power
supply are high enough (around ±4 V) to permit proper recep-
tion by an EIA 232–E receiver, and can be used in applications
where strict compliance to EIA 232–E is not required.
Another requirement of the ML145406 drivers is that they
withstand a short to another driver in the EIA 232–E cable.
The worst–case condition that is permitted by EIA 232–E is a
±15V source that is current limited to 500 mA. The ML145406
drivers can withstand this condition momentarily. In most short
circuit conditions the source driver will have a series 300
Ω
output impedance needed to satisfy the EIA 232–E driver
requirements. This will reduce the short circuit current to
under 40 mA which is an acceptable level for the ML145406
to withstand.
Unlike some other drivers, the ML145406 drivers feature an
internally–limited output slew–rate that does not exceed 30 V
per µs.
RECEIVERS
The job of an EIA 232–E receiver is to level–shift voltages
in the range of – 25 to + 25 V down to TTL/CMOS logic lev-
els (0 to + 5 V). A voltage of between – 3 and – 25 V on Rx1
is defined as a mark and produces a logic 1 at DO1. A voltage
between + 3 and + 25 V is a space and produces a logic zero.
While receiving these signals, the Rx inputs must present a
resistance between 3 and 7 kΩ. Nominally, the input resistance
of the Rx1–Rx3 inputs is 5.4 kΩ.
The input threshold of the Rx1–Rx3 inputs is typically
biased at 1.8 V above ground (GND) with typically 800 mV of
hysteresis included to improve noise immunity. The 1.8 V bias
forces the appropriate DO pin to a logic 1 when its Rx input is
open or grounded as called for in the EIA 232–E specification
Notice that TTL logic levels can be applied to the Rx inputs in
lieu of normal EIA 232–E signal levels. This might be helpful
in situations where access to the modem or computer through
the EIA 232–E connector is necessary with TTL devices.
However, it is important not to connect the EIA 232–E outputs
(Tx1–Tx3) to TTL inputs since TTL operates off + 5 V only,
and may be damaged by the high output voltage of the
ML145406.
The DO outputs are to be connected to a TTL or CMOS
input (such as an input to a modem chip). These outputs will
swing from VCC to ground, allowing the designer to operate
the DO and DI pins from digital power supply. The Tx and Rx
sections are independently powered by VDD andVSS so that
one may run logic at + 5 V and the EIA 232–E signals at ±12V
POWER
SUPPLY CONSIDERATIONS
Figure 4 shows a technique to guard against excessive devic
current.
The diode D1 prevents excessive current from flowing
through an internal diode from the VCC pin to the VDD pin
when VDD < VCC by approximately 0.6 V. This high current
condition can exist for a short period of time during
powerup/down. Additionally, if the + 12 V supply is switched
off while the + 5 V is on and the off supply is a low impedanc
to ground, the diode D1 will prevent current flow through the
internal diode.
The diode D2 is used as a voltage clamp, to prevent VSS
from drifting positive to VCC, in the event that power is
removed from VSS (Pin 12). If VSS power is removed, and the
impedance from the VSS pin to ground is greater than approxi
mately 3 kΩ, this pin will be pulled to VCC by internal circuit
ry causing excessive current in the VCC pin.
If by design, neither of the above conditions are allowed to
exist, then the diodes D1 and D2 are not required.
ESD PROTECTION
ESD protection on IC devices that have their pins accessible
to the outside world is essential. High static voltages applied t
the pins when someone touches them either directly or indi-
rectly can cause damage to gate oxides and transistor junction
by coupling a portion of the energy from the I/O pin to the
power supply buses of the IC. This coupling will usually occur
through the internal ESD protection diodes. The key to protect
ing the IC is to shunt as much of the energy to ground as pos-
sible before it enters the IC. Figure 4 shows a technique which
will clamp the ESD voltage at approximately ±15 V using the
MMVZ15VDLT1. Any residual voltage which appears on the
supply pins is shunted to ground through the capacitors
C1–C3. This scheme has provided protection to the interface
part up to ±10kV, using the human body model test.
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