DATASHEET
ISL6115, ISL6116, ISL6117, ISL6120
Power Distribution Controllers
This family of fully featured hot swap power controllers
targets applications in the +2.5V to +12V range. The
ISL6115 is for +12V control, the ISL6116 for +5V, the
ISL6117 for +3.3V and the ISL6120 for +2.5V control
applications. Each has a hard wired undervoltage (UV)
monitoring and reporting threshold level approximately
80% of the aforementioned voltage.
The ISL6115 has an integrated charge pump allowing
control of up to +16V rails using an external N-Channel
MOSFET whereas the other devices utilize the +12V
bias voltage to fully enhance the N-Channel pass FET.
All ICs feature programmable overcurrent (OC)
detection, current regulation (CR) with time delay to
latch-off and soft-start.
The current regulation level is set by 2 external
resistors; R
ISET
sets the CR Vth and the other is a low
ohmic sense element across, which the CR Vth is
developed. The CR duration is set by an external
capacitor on the CTIM pin, which is charged with a
20µA current once the CR Vth level is reached. If the
voltage on the CTIM capacitor reaches 1.9V the IC then
quickly pulls down the GATE output latching off the
pass FET.
This family although designed for high side switch
control the ISL6116, ISL6117, ISL6120 can also be
used in a low side configuration for control of much
higher voltage potentials.
FN9100
Rev 8.00
December 3, 2015
Features
• HOT SWAP Single Power Distribution Control
(ISL6115 for +12V, ISL6116 for +5V, ISL6117 for
+3.3V and ISL6120 for +2.5V)
• Overcurrent Fault Isolation
• Programmable Current Regulation Level
• Programmable Current Regulation Time to
Latch-Off
• Rail-to-Rail Common Mode Input Voltage Range
(ISL6115)
• Internal Charge Pump Allows the Use of N-Channel
MOSFET for +12V Control (ISL6115)
• Undervoltage and Overcurrent Latch Indicators
• Adjustable Turn-On Ramp
• Protection During Turn-On
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
• 1µs Response Time to Dead Short
• Pb-Free Available (RoHS Compliant)
Applications
• Power Distribution Control
• Hot Plug Components and Circuit
Application Circuits- High Side
Controller
+
LOAD
-
Application Two - Low Side
Controller
+VBUS
LOAD
1
2
3
4
8
ISL6115
ISL6116
ISL6117
ISL6120
PWRON
7
6
OC
5
4
3
2
1
PGOOD
ISL6116
ISL6117
ISL6120
5
6
7
8
PWRON
+V SUPPLY TO BE CONTROLLED
+12V
12V REG
OC
FN9100 Rev 8.00
December 3, 2015
Page 1 of 14
ISL6115, ISL6116, ISL6117, ISL6120
Simplified Block Diagram
V
DD
+
I
SET
-
+
+
-
I
SEN
UV
-
+
-
POR
8V
QN R
R
Q
S
PWRON
V
REF
ENABLE
12V
PGOOD
20µA
CLIM
+
-
-
+
WOCLIM
ENABLE
20µA
RISING
EDGE
PULSE
V
DD
7.5k
+
-
1.86V
+
-
ISL61xx
UV DISABLE
OC
GATE
10µA
18V
FALLING
EDGE
DELAY
CTIM
V
SS
18V
Ordering Information
PART
NUMBER
ISL6115CBZA (Notes 1, 2)
ISL6116CBZA (Notes 1, 2)
No longer available or
supported
ISL6117CBZA (Notes 1, 2)
ISL6120CBZA (Notes 1, 2)
No longer available or
supported
ISL6115EVAL1Z
NOTES:
1. Please refer to
TB347
for details on reel specifications. Add “-T” suffix for tape and reel.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL6115.
For more information on MSL please see
techbrief
TB363.
PART
MARKING
6115 CBZ
6116 CBZ
TEMP.
RANGE (°C)
0 to +85
0 to +85
PACKAGE
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
PKG.
DWG. #
M8.15
M8.15
6117 CBZ
6120 CBZ
0 to +85
0 to +85
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
M8.15
M8.15
Evaluation Platform
FN9100 Rev 8.00
December 3, 2015
Page 2 of 14
ISL6115, ISL6116, ISL6117, ISL6120
Pin Configuration
ISL6115, ISL6116, ISL6117, ISL6120
(8 LD SOIC)
TOP VIEW
ISET
ISEN
GATE
VSS
1
2
3
4
8 PWRON
7 PGOOD
6 CTIM
5 VDD
Pin Descriptions
PIN # SYMBOL
1
2
3
ISET
ISEN
GATE
FUNCTION
Current Set
Current Sense
External FET Gate
Drive Pin
Chip Return
Chip Supply
Current Limit Timing
Capacitor
12V chip supply. This can be either connected directly to the +12V rail supplying the
switched load voltage or to a dedicated V
SS
+12V supply.
Connect a capacitor from this pin to ground. This capacitor determines the time delay
between an overcurrent event and chip output shutdown (current limit time-out). The
duration of current limit time-out is equal to 93k x C
TIM
.
DESCRIPTION
Connect to the low side of the current sense resistor through the current limiting set
resistor. This pin functions as the current limit programming pin.
Connect to the more positive end of sense resistor to measure the voltage drop across this
resistor.
Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to
ground sets the turn-on ramp. At turn-on this capacitor will be charged to V
DD
+5V
(ISL6115) and to V
DD
(ISL6116, ISL6117, ISL6120) by a 10µA current source.
4
5
6
VSS
VDD
CTIM
7
PGOOD
Power Good Indicator Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open
drain N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less
than the UV level for the particular IC.
Power-ON
PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is
driven high to a maximum of 5V or is left open. Do not drive this input >5V. After a
current limit time-out, the chip is reset by a low level signal applied to this pin. This
input has 20µA pull-up capability.
8
PWRON
FN9100 Rev 8.00
December 3, 2015
Page 3 of 14
ISL6115, ISL6116, ISL6117, ISL6120
Absolute Maximum Ratings
T
A
= +25°C
V
DD
. . . . . . . . . . . . . . . . . .
GATE . . . . . . . . . . . . . . . . .
ISEN, PGOOD, PWRON, CTIM,
ESD Rating
Human Body Model . . . . . .
. . . . . . . . . . . -0.3V to +16V
. . . . . . . . . -0.3V to V
DD
+ 8V
ISET . . . -0.3V to V
DD
+ 0.3V
. . . . . . . . . . . . . . . . . . . 5kV
Thermal Information
Thermal Resistance (Typical, Note 4)
JA
(°C/W)
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . .
98
Maximum Junction Temperature (Plastic Package) . . +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
V
DD
Supply Voltage Range (ISL6115) . . . . . . . . +12V ±15%
V
DD
Supply Voltage Range (ISL6116, 17, 20) . . +12V ±25%
Temperature Range (T
A
) . . . . . . . . . . . . . . . . 0°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
V
DD
= 12V, T
A
= T
J
= 0°C to +85°C, Unless Otherwise Specified. Temperature limits
established by characterization and are not production tested.
Boldface limits apply over the
operating temperature range, -40°C to +85°C.
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7) UNITS
PARAMETER
CURRENT CONTROL
ISET Current Source
ISET Current Source
Current Limit Amp Offset Voltage
Current Limit Amp Offset Voltage
GATE DRIVE
GATE Response Time to Severe OC
GATE Response Time to Overcurrent
GATE Turn-On Current
GATE Pull-Down Current
GATE Pull-Down Current (Note 6)
ISL6115 Undervoltage Threshold
ISL6115 GATE High Voltage
ISL6116 Undervoltage Threshold
ISL6117 Undervoltage Threshold
ISL6120 Undervoltage Threshold
ISL6116, ISL6117, ISL6120 GATE
High Voltage
BIAS
V
DD
Supply Current
V
DD
POR Rising Threshold
V
DD
POR Falling Threshold
V
DD
POR Threshold Hysteresis
Maximum PWRON Pull-Up Voltage
I
ISET_ft
I
ISET_pt
Vio_ft
Vio_pt
T
J
= +15°C to +55°C
V
ISET
- V
ISEN
V
ISET
- V
ISEN,
T
J
= +15°C to
+55°C
18.5
19
-6
-2
20
20
0
0
21.5
21
6
2
µA
µA
mV
mV
pd_woc_amp
pd_oc_amp
I
GATE
OC_GATE_I_4V
V
GATE
to 10.8V
V
GATE
to 10.8V
V
GATE
to = 6V
Overcurrent
-
-
8.4
45
0.5
9.2
100
600
10
75
0.8
9.6
-
-
11.6
-
-
10
-
4.5
2.8
1.9
-
ns
ns
µA
mA
A
V
V
V
V
V
V
WOC_GATE_I_4V Severe Overcurrent
12V
UV_VTH
12VG
5V
UV_VTH
3V
UV_VTH
2V
UV_VTH
VG
GATE Voltage
GATE Voltage
V
DD
+ 4.5V
V
DD
+ 5V
4.0
2.4
1.8
V
DD
- 1.5V
4.35
2.6
1.85
V
DD
I
VDD
V
DD_POR_L2H
V
DD_POR_H2L
V
DD_POR_HYS
PWRN_PUV
VDD Low to High
VDD High to Low
V
DD_POR_L2H -
V
DD_POR_H2L
Maximum External Pull-up
Voltage
-
7.8
7.5
0.1
-
3
8.4
8.1
0.3
5
5
9
8.7
0.6
-
mA
V
V
V
V
FN9100 Rev 8.00
December 3, 2015
Page 4 of 14
ISL6115, ISL6116, ISL6117, ISL6120
Electrical Specifications
V
DD
= 12V, T
A
= T
J
= 0°C to +85°C, Unless Otherwise Specified. Temperature limits
established by characterization and are not production tested.
Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PWRN_V
PWR_Vth
PWR_hys
PWRN_I
TEST CONDITIONS
PWRON Pin Open
MIN
(Note 7)
2.7
1.4
130
9
TYP
3.2
1.7
170
17
MAX
(Note 7) UNITS
-
2.0
250
25
V
V
mV
µA
PARAMETER
PWRON Pull-Up Voltage
PWRON Rising Threshold
PWRON Hysteresis
PWRON Pull-Up Current
CURRENT REGULATION DURATION/POWER GOOD
C
TIM
Charging Current
C
TIM
Fault Pull-Up Current (Note 6)
Current Limit Time-Out Threshold
Voltage
Power Good Pull Down Current
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
C
TIM
_Vth
PG_Ipd
CTIM Voltage
V
OUT
= 0.5V
C
TIM
_ichg0
V
CTIM
= 0V
16
-
1.3
-
20
20
1.8
8
23
-
2.3
-
µA
mA
V
mA
Description and Operation
The members of this IC family are single power supply
distribution controllers for generic hot swap
applications across the +2.5V to +12V supply range.
The ISL6115 is targeted for +12V switching
applications whereas the ISL6116 is targeted for +5V,
the ISL6117 for +3.3V and the ISL6120 for +2.5V
applications. Each IC has a hardwired undervoltage
(UV) threshold level approximately 17% lower than the
stated voltages.
These ICs feature a highly accurate programmable
current regulation (CR) level with programmable time
delay to latch-off, and programmable soft-start
turnHon ramp all set with a minimum of external
passive components. The ICs also include severe OC
protection that immediately shuts down the MOSFET
switch should a rapid load current transient such as
with a dead short cause the CR Vth to exceed the
programmed level by 150mV. Additionally, the ICs
have a UV indicator and an OC latch indicator. The
functionality of the PGOOD feature is enabled once
the IC is biased, monitoring and reporting any UV
condition on the ISEN pin.
Upon initial power-up, the IC can either isolate the
voltage supply from the load by holding the external
N-Channel MOSFET switch off or apply the supply rail
voltage directly to the load for true hot swap capability.
The PWRON pin must be pulled low for the device to
isolate the power supply from the load by holding the
external N-Channel MOSFET off. With the PWRON pin
held high or floating the IC will be in true hot swap
mode. In both cases the IC turns on in a soft-start
mode protecting the supply rail from sudden in-rush
current.
At turn-on, the external gate capacitor of the N-
Channel MOSFET is charged with a 10µA current
source resulting in a programmable ramp (soft-start
turn-on). The internal ISL6115 charge pump supplies
the gate drive for the 12V supply switch driving that
gate to ~V
DD
+5V, for the other three ICs the gate
drive voltage is limited to the chip bias voltage, VDD.
Load current passes through the external current
sense resistor. When the voltage across the sense
resistor exceeds the user programmed CR voltage
threshold value, (see Table 1 for R
ISET
programming
resistor value and resulting nominal current regulation
threshold voltage, V
CR
) the controller enters its
current regulation mode. At this time, the time-out
capacitor, on CTIM pin is charged with a 20µA current
source and the controller enters the current limit time
to latch-off period. The length of the current limit time
to latch-off duration is set by the value of a single
external capacitor (see Table 2) for C
TIM
capacitor
value and resulting nominal current limited time-out
to latch-off duration placed from the CTIM pin (pin 6)
to ground. The programmed current level is held until
either the OC event passes or the time-out period
expires. If the former is the case then the N-Channel
MOSFET is fully enhanced and the C
TIM
capacitor is
discharged. Once C
TIM
charges to 1.87V signaling
that the time-out period has expired, an internal latch
is set whereby the FET gate is quickly pulled to 0V
turning off the N-Channel MOSFET switch, isolating
the faulty load.
FN9100 Rev 8.00
December 3, 2015
Page 5 of 14
京公网安备 11010802033920号
EEWORLD
