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CD2481: DescriptionProgrammable Four-Channel Communications Controller; File Size974KB，222 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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CD2481 Overview

Programmable Four-Channel Communications Controller

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CD2481

Programmable Four-Channel Communications Controller

Datasheet

The CD2481 is a four-channel synchronous/asynchronous communications controller

specifically designed to reduce host-system processing overhead and increase efficiency in a

wide variety of communications applications. A special member of the CD24X1 family, the

device allows easy field upgrades and enhancement with an on-chip 8K-word microcode store

for downloaded control code. The CD2481 is packaged in a 100-pin MQFP package that offers

10 data/clock/modem pins per channel. The device has four fully independent serial channels to

support standard asynchronous, PPP, MNP



4, SLIP, bit-synchronous (HDLC), and byte-

synchronous (bisync, X.21) protocols.

The device is non-functional until the microcode is

downloaded; only a small boot ROM with code to perform device initialization is included.

The device is based on a proprietary on-chip RISC processor that performs all the time-critical,

low-level tasks otherwise performed by the host system.

The CD2481 boosts system efficiency with eight on-chip DMA channels, on-chip FIFOs (16

bytes/direction), intelligent vectored interrupts, and intelligent protocol processing. The on-chip

DMA controller provides ‘fire-and-forget’ transmit support — the host need only inform the

CD2481 of the location of the packet to send. Similarly, on receive, the CD2481 automatically

receives a complete packet with no host intervention or assistance. The DMA controller also has

a transmit ‘Append mode’ for use in asynchronous applications.

The DMA controller uses a dual-buffer scheme that easily implements simple or complex buffer

schemes. Each channel and direction in the dual-buffer scheme has two active buffers.

The CD2481 can be programmed to interrupt the host at the completion of a frame or buffer. In

applications where buffers are of a small, fixed size, the dual-buffer scheme allows large frames

to be divided into multiple buffers.

For applications where a DMA interface is not desired, the device can be operated as either

interrupt-driven or polled. This choice is available for each channel and each direction. For

example, a channel can be programmed for DMA transmit and interrupt-driven receive. In either

case, 16-byte FIFOs on each channel and in each direction reduce latency time requirements,

making both software and hardware designs less time-critical. Threshold levels on the FIFOs are

user-programmable.

Vectored interrupts are another way the CD2481 helps system efficiency. Separate interrupts are

generated for transmit, receive, and modem-signal/timer changes with unique, user-defined

vectors for each type and channel. This allows very flexible interfacing and fast, efficient

interrupt coding. For example, the Good Data



interrupt allows the host to vector directly to a

routine that transfers the receive data — no status or error checking is required.

As of May 2001, this document replaces the Basis Communications Corp.

document

CL-CD2481 — Programmable Four-Channel Communications Controller.

May 2001

Programmable Four-Channel Communications Controller — CD2481

Contents

1.0

Features

......................................................................................................................... 9

1.1

1.2

Benefits ...............................................................................................................11

CD2XXX Device Family Compatibility.................................................................12

Abbreviations.......................................................................................................13

Acronyms ............................................................................................................14

Pin Diagram — CD2481......................................................................................15

Pin Functions — CD2481....................................................................................16

Pin Descriptions ..................................................................................................16

Memory Map .......................................................................................................20

4.1.1 Global Registers.....................................................................................20

4.1.2 Option Registers.....................................................................................21

4.1.3 Bit Rate and Clock Option Registers......................................................22

4.1.4 Channel Command and Status Registers ..............................................22

4.1.5 Interrupt Registers..................................................................................22

4.1.6 DMA Registers .......................................................................................24

4.1.7 Timer Registers ......................................................................................25

4.2.1 Global Registers.....................................................................................25

4.2.2 Option Registers.....................................................................................25

4.2.3 Bit Rate and Clock Option Registers......................................................29

4.2.4 Channel Command and Status Registers ..............................................29

4.2.5 Interrupt Registers..................................................................................31

4.2.6 DMA Registers .......................................................................................34

4.2.7 Timer Registers ......................................................................................35

Host Interface ......................................................................................................37

5.1.1 Host Read and Write Cycles ..................................................................37

5.1.2 Byte and Word Transfers .......................................................................39

Interrupts .............................................................................................................39

5.2.1 Contexts and Channels ..........................................................................40

5.2.2 Interrupt Registers..................................................................................40

5.2.3 Groups and Types..................................................................................41

5.2.4 Hardware Signals and IACK Cycles .......................................................42

FIFO and Timer Operations ................................................................................44

5.3.1 Receive FIFO Operation ........................................................................44

5.3.2 Transmit FIFO Operation .......................................................................44

5.3.3 Timers ....................................................................................................44

5.3.4 Timers in Synchronous Protocols...........................................................45

5.3.5 Timers in Asynchronous Protocols.........................................................45

5.3.6 Transmit Timer .......................................................................................45

2.0

Conventions

...............................................................................................................13

2.1

2.2

3.0

Pin Information

..........................................................................................................15

3.1

3.2

3.3

4.0

................................................................................................20

4.1

4.2

5.0

Functional Description

...........................................................................................37

5.1

5.2

5.3

Datasheet

CD2481 — Programmable Four-Channel Communications Controller

5.4

5.5

5.6

DMA Operation ................................................................................................... 45

5.4.1 Bus Acquisition Cycle............................................................................. 46

5.4.2 DMA Data Transfer ................................................................................ 46

5.4.3 Bus Error Handling................................................................................. 47

5.4.4 A and B Buffers and Chaining ................................................................ 48

5.4.5 Transmit DMA Transfer .......................................................................... 49

5.4.6 Synchronous Transmitter Examples ...................................................... 50

5.4.7 Receive DMA Transfer ........................................................................... 52

Bit Rate Generation and Data Encoding ............................................................. 60

Hardware Configurations .................................................................................... 67

5.6.1 Interface to a 32-Bit Data Bus ................................................................ 68

5.6.2 DMA Connections for the CD2481 ......................................................... 68

5.6.3 Recommended CD2481 as a DTE and DCE Interface .......................... 68

Microcode Download Information........................................................................ 70

6.1.1 Registers Specific to Download Operations ........................................... 70

6.1.2 Download Code Example....................................................................... 71

HDLC Processing................................................................................................ 75

7.1.1 FCS (Frame Check Sequence) .............................................................. 75

7.1.2 HDLC Transmit Mode............................................................................. 75

7.1.3 HDLC Receive Mode ............................................................................. 76

PPP (Point-to-Point Protocol) Mode.................................................................... 77

7.2.1 Character Format ................................................................................... 77

7.2.2 Frame Format ........................................................................................ 77

7.2.3 FCS (Frame Check Sequence) .............................................................. 77

7.2.4 Transparency ......................................................................................... 78

7.2.5 Definition of a Valid Frame..................................................................... 79

7.2.6 Transmitter ............................................................................................. 79

7.2.7 Receiver ................................................................................................. 80

SLIP Processing.................................................................................................. 81

7.3.1 Framing .................................................................................................. 81

7.3.2 Debugging Aids ...................................................................................... 82

MNP4‚/ARAP Protocol Processing...................................................................... 82

7.4.1 Framing .................................................................................................. 82

7.4.2 MNP4‚/ARAP FCS (Frame Check Sequence) Calculation..................... 83

Async Processing................................................................................................ 83

7.5.1 Transmitter In-Band Flow Control .......................................................... 83

7.5.2 Receiver In-Band Flow Control .............................................................. 84

7.5.3 Out-of-Band Flow Control ...................................................................... 85

7.5.4 Line Break Detection and Generation .................................................... 86

7.5.5 Special Character Transmission ............................................................ 86

7.5.6 Special Character Recognition............................................................... 87

7.5.7 Special Character Range ....................................................................... 87

7.5.8 UNIX Support Features .......................................................................... 88

Bisync Protocol ................................................................................................... 92

7.6.1 Bisync Transmit Processing................................................................... 92

7.6.2 Bisync Receive Processing.................................................................... 92

6.0

Microcode Download

.............................................................................................. 70

6.1

7.0

Protocol Processing

............................................................................................... 75

7.1

7.2

7.3

7.4

7.5

7.6

Datasheet

Programmable Four-Channel Communications Controller — CD2481

7.7

7.8

7.9

7.10

7.6.3 CRC Calculation in Bisync Mode ...........................................................93

7.6.4 BCC Computation Formulas ..................................................................94

7.6.5 Receive State Tables .............................................................................95

X.21 Call Set-Up Mode........................................................................................97

7.7.1 X.21 Transmit .........................................................................................97

7.7.2 X.21 Receive ..........................................................................................97

Extended X.21 Mode...........................................................................................99

7.8.1 Extended X.21 Transmit.........................................................................99

7.8.2 Extended X.21 Receive..........................................................................99

Programmable Sync..........................................................................................100

7.9.1 Programmable Sync Transmit..............................................................101

7.9.2 Programmable Sync Receive...............................................................101

Non-8-Bit Data Transfers ..................................................................................102

Global Initialization ............................................................................................105

Async Interrupt Setup Example.........................................................................107

HDLC DMA Channel Setup Example................................................................107

Receive DMA Interrupt Service Routine............................................................109

Transmit Interrupt Service Routine....................................................................110

Support Files from the Intel FTP Server............................................................110

Global Registers................................................................................................112

9.1.1 Global Firmware Revision Code Register (GFRCR) ............................112

9.1.2 Channel Access Register (CAR) ..........................................................112

Option Registers................................................................................................113

9.2.1 Channel Mode Register (CMR) ............................................................113

9.2.2 Channel Option Register 1 (COR1)......................................................114

9.2.3 Channel Option Register 2 (COR2)......................................................116

9.2.4 Channel Option Register 3 (COR3)......................................................123

9.2.5 Channel Option Register 4 (COR4)......................................................130

9.2.6 Channel Option Register 5 (COR5)......................................................131

9.2.7 Channel Option Register 6 (COR6)......................................................132

9.2.8 Channel Option Register 7 (COR7)......................................................135

9.2.9 Special Character Registers –

Async and Programmable Sync Modes136

9.2.10 Special Character Range – Async Mode Only .....................................138

9.2.11 LNext Character (LNXT) – Async Mode Only ......................................139

9.2.12 Receive Frame Address Registers – HDLC Sync Mode Only .............139

9.2.13 CRC Polynomial Select Register (CPSR) ............................................141

9.2.14 Transmit Special Mapped Characters – PPP Mode only .....................141

9.2.15 Transmit Async Control Character Maps –

Async-HDLC/PPP Mode Only142

9.2.16 Receive Async Control Character Maps –

Async-HDLC/PPP Mode Only143

Bit Rate and Clock Option Registers.................................................................145

9.3.1 Receive Baud Rate Generator Registers .............................................145

9.3.2 Transmit Baud Rate Generator Registers ............................................146

Channel Command and Status Registers .........................................................148

9.4.1 Channel Command Register (CCR) .....................................................148

8.0

Programming Examples

......................................................................................103

8.1

8.2

8.3

8.4

8.5

8.6

9.0

Detailed Register Descriptions

........................................................................112

9.1

9.2

9.3

9.4

Datasheet

CD2481 Related Products

	CD2481	SCD248110QCD
Description	Programmable Four-Channel Communications Controller	Programmable Four-Channel Communications Controller

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