Preliminary
RT9210
Dual 5V Synchronous Buck DC-DC PWM Controller
for DDR Memory V
DDQ
and V
TT
Termination
General Description
The RT9210 is a dual high power, high efficiency
synchronous buck DC-DC controller optimized for high
performance double data rate (DDR) memory applications.
It is designed to convert voltage supplies ranging from
4.5V to 5.5V into efficiently 2.5V
DDQ
for powering DDR
memory, V
TT
for signal termination and a buffered amplifier
for V
REF
reference. V
TT
tracks (V
DDQ
/2) to ±30mV, and
V
TT
accurately tracks V
REF
. The RT9210 integrates all of
the control, output adjustment, monitoring and protection
functions into a single package.
The V
TT
supply can be turned off independently of V
DDQ
during S3 sleep mode, the V
TT
output is maintained by a
low power window regulator when V2_SD pin being
triggered high.
The RT9210 provides simple, single feedback loop, voltage
mode control with fast transient response for V
DDQ
regulator. The V
TT
regulator features internal compensation
that eases the circuitry design. It includes two phase-
locked 300kHz sawtooth-wave oscillators which are placed
90° to minimize interference between the two PWM
regulators.
The RT9210 protects against over-current conditions by
inhibiting PWM operation. It also monitors the current in
the V
DDQ
regulator by using the R
DS(ON)
of the upper
MOSFET which eliminates the need for a current sensing
resistor.
Features
Operating with Single 5V Supply Voltage
High Power V
DDQ
, V
TT
and V
REF
for DDR Memory
V
TT
Tracks (V
DDQ
/2) to ±30mV
V
TT
Regulator Internally Compensated
Support
“
S3
”
Sleep Mode
Drives All Low Cost N-MOSFETs
Voltage Mode PWM Control
300kHz Fixed Frequency Oscillator
Fast Transient Response :
Full 0% to 100% Duty Ratio
Internal Soft-Start
Adaptive Non-Overlapping Gate Driver
Over-Current Fault Monitor on V
CC
, No Current
Sense Resistor Required
RoHS Compliant and 100% Lead (Pb)-Free
Applications
DDR Memory Termination Supply
SSTL_2 and SSTL_3 Interfaces
Graph Card, Motherboard, Desktop Servers
High Power Tracking DC-DC Regulators
Pin Configurations
(TOP VIEW)
UGATE1
BOOT1
PHASE1
VREF
FB1
COMP1
SENSE1
VREF_IN
GNDA
NC
BOOT2
UGATE2
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PGND1
LGATE1
PVCC1
OCSET/SD
V2_SD
PGOOD
NC
SENSE2
NC
VCC
LGATE2
PGND2
Ordering Information
RT9210
Package Type
C : TSSOP-24
S : SOP-24
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
Note :
TSSOP-24 & SOP-24
RichTek Pb-free and Green products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
100% matte tin (Sn) plating.
DS9210-05 March 2007
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1
RT9210
Typical AppIication Circuit
V
IN
2.5V/3.3V/5V
Preliminary
V
CC
5V
V
IN
(>
V
DDQ
)
+
R1
3.48k
C1
1nF
C2
1uF
R6
10k
D1
1N4148
C9
0.1uF
C10
470uF
2.5V/3.3V/5V
RT9210
RESET
Q5
15
21
7
VTT_SD
VREF_IN
C3 100pF
C4
0.1uF
C6
VREF_OUT
100pF
C5
5.6nF
R4
6.34k
20
8
4
VCC
OCSET/SD
SENSE1
V2_SD
VREF_IN
VREF
PGOOD
BOOT1
19
2
PHKD6N02LT
Q1
1uH
C12 to C15
L1
150uF (x 4)
+
V
DDQ
1.8V
6 COMP1
UGATE1 1
3
PHASE1
22
PVCC1
23
LGATE1
24
PGND1
BOOT2
UGATE2
PHASE2
11
12
10
14
13
Q2
D2
1N4148
C11
0.1uF
V
CC
5V
PHKD6N02LT
Q3
1uH
C16 to C17
L2
150uF (x 2)
+
5
C7
0.1uF
R2
1k
R3
1.25k
C8
15nF
R5
100
FB1
LGATE2
PGND2
SENSE2 17
GNDA
9
V
TT
0.9V
Q4
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DS9210-05 March 2007
Preliminary
Functional Pin Description
UGATE1 (Pin 1)
V
DDQ
upper gate driver output. Connect to gate of the high-
side power N-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
BOOT1 (Pin 2)
Bootstrap supply pin for the upper gate driver. Connect
the bootstrap capacitor between BOOT1 pin and the
PHASE1 pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET.
PHASE1 (Pin 3)
Connect this pin to the source of the upper MOSFET and
the drain of the lower MOSFET. PHASE1 is used to
monitor the voltage drop across the upper MOSFET of
the V
DDQ
regulator for over-current protection.
VREF (Pin 4)
Buffered internal reference voltage of V
DDQ
/ 2. This output
should be used to provide the reference voltage for the
Northbridge chipset and DDR memory.
FB1 (Pin 5)
V
DDQ
feedback voltage. This pin is the inverting input of
the error amplifier. FB1 senses the V
DDQ
through an
external resistor divider network.
COMP1 (Pin 6)
V
DDQ
external compensation. This pin internally connects
to the output of the error amplifier and input of the PWM
comparator. Use a RC + C network at this pin to
compensate the feedback loop to provide optimum
transient response.
SENSE1 (Pin 7)
This pin is connected directly to the regulated output of
V
DDQ
supply. This pin is also used as an input to create
the voltage at V
REF.
VREF_IN (Pin 8)
RT9210
This pin is used as an option to overdrive the internal
resistor divider network that sets the voltage for both V
REF
and the reference voltage for the V
TT
supply. A 100pF
capacitor between VREF_IN and ground is recommended
for proper operation.
GNDA (Pin 9)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. Ties the pin directly to ground
plane with the lowest impedance.
BOOT2 (Pin 11)
Bootstrap supply pin for the upper gate driver. Connect
the bootstrap capacitor between BOOT2 pin and the
PHASE2 pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET.
UGATE2 (Pin 12)
V
TT
upper gate driver output. Connect to gate of the high-
side power N-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
PGND2 (Pin 13)
Return pin for high currents flowing in low-side power
N-MOSFET. Ties the pin directly to the low-side MOSFET
source and ground plane with the lowest impedance.
LGATE2 (Pin 14)
V
TT
lower gate driver output. Connect to gate of the low-
side power N-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the lower MOSFET has turned off.
VCC (Pin 15)
Connect this pin to a well-decoupled 5V bias supply. It is
also the positive supply for the lower gate driver, LGATE2.
DS9210-05 March 2007
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3
RT9210
NC (Pin 10 , 16 , 18)
No internal connection.
SENSE2 (Pin 17)
Preliminary
LGATE1 (Pin 23)
V
DDQ
lower gate drive output. Connect to gate of the low-
side power N-MOSFET. This pin is monitored by the
adaptive shoot-through protection circuitry to determine
when the lower MOSFET has turned off.
PGND1 (Pin 24)
Return pin for high currents flowing in low-side power
N-MOSFET. Ties the pin directly to the low-side MOSFET
source and ground plane with the lowest impedance.
This pin is connected directly to the regulated output of
V
TT
supply. This pin is also used as the feedback pin of
the V
TT
regulator and as the regulation point for the window
regulator that is enable in V2_SD mode.
PGOOD (Pin 19)
PGOOD is an open-drain output used to indicate that both
the V
DDQ
and V
TT
regulators are within normal operating
voltage ranges.
V2_SD (Pin 20)
A TTL compatible high level at this pin puts the V
TT
controller into“sleep”mode. In sleep mode, both UGATE2
and LGATE2 are driven low, effectively floating the V
TT
supply. While the V
TT
supply
“floats”,
it is held to about
50% of V
DDQ
via a low current window regulator which
drivers V
TT
via the SENSE2 pin. The window regulator
can overcome up to at least
±10mA
of leakage on V
TT
.
While V2_SD is high, PGOOD is low.
OCSET/SD (Pin 21)
Connect a resistor (R
OCSET
) from this pin to the drain of
the upper MOSFET of the V
DDQ
regulator sets the over-
current trip point. R
OCSET
, an internal 40μA current source
, and the upper MOSFET on-resistance, R
DS(ON)
, set the
V
DDQ
converter over-current trip point (I
OCSET
) according
to the following equation:
I
OCSET
=
40uA
×
R
OCSET
R
DS(ON)
of the upper MOSFET
An over-current trip cycles the soft-start function. Pulling
the pin to ground resets the device and all external
MOSFETs are turned off allowing the two output voltage
power rails to float.
PVCC1 (Pin 22)
Connect this pin to a well-decoupled 5V supply. It is also
the positive supply for the lower gate driver, LGATE1.
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4
DS9210-05 March 2007
Preliminary
Function Block Diagram
RT9210
VCC
137.5%
0.8V
Ref.
0.8V
FB1
62.5%
OVP
&
UVP
OV
UV
Power
On
Reset
POR
Bias
OC
Thermal
SHDN
40uA
OCSET/SD
Soft-
Start
1
BOOT1
+
-
OC
OV
UV
Thermal
SHDN
Control
Logic
PWM1
UGATE1
PHASE1
PVCC1
LGATE1
PGND1
300kHz
Oscillator
-
+
OC
90 deg
OV
UV
shift
Thermal
SHDN
Control
Logic
VCC
UGATE2
BOOT2
PWM2
PGND2
LGATE2
PGOOD
Power
Good
+ +
EA
-
COMP1
VREE_IN
SENSE1
SENSE2
Window
Regulator
V2_SD
DS9210-05 March 2007
+
VREF
200k
200k
Zf
FB2
+
EA
-
Zc
GNDA
+
-
-
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