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FDN352AP Single P-Channel, PowerTrench
®
MOSFET
August 2005
FDN352AP
Single P-Channel, PowerTrench
®
MOSFET
Features
■
–1.3 A, –30V
–1.1 A, –30V
R
DS(ON)
= 180 m
Ω
@ V
GS
= –10V
R
DS(ON)
= 300 m
Ω
@ V
GS
= –4.5V
■
High performance trench technology for extremely low
R
DS(ON)
.
■
High power version of industry Standard SOT-23 package.
Identical pin-out to SOT-23 with 30% higher power handling
capability.
General Description
This P-Channel Logic Level MOSFET is produced using Fair-
child Semiconductor advanced Power Trench process that has
been especially tailored to minimize the on-state resistance and
yet maintain low gate charge for superior switching perfor-
mance.
These devices are well suited for low voltage and battery pow-
ered applications where low in-line power loss is needed in a
very small outline surface mount package.
Applications
■
Notebook computer power management
D
D
S
G
G
S
SuperSOT™-3
Absolute Maximum Ratings
T
A
= 25°C unless otherwise noted
Symbol
V
DSS
V
GSS
I
D
P
D
T
J
, T
STG
R
θ
JA
R
θ
JC
Drain-Source Voltage
Gate-Source Voltage
Drain Current
– Continuous
– Pulsed
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
Operating and Storage Junction Temperature Range
(Note 1a)
Parameter
Ratings
–30
±
25
–1.3
–10
0.5
0.46
–55 to +150
Units
V
V
A
W
°
C
°
C/W
Thermal Characteristics
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
250
75
Package Marking and Ordering Information
Device Marking
52AP
Device
FDN352AP
Reel Size
7’’
Tape width
8mm
Quantity
3000 units
©2005 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
FDN352AP Rev. C1
FDN352AP Single P-Channel, PowerTrench
®
MOSFET
Electrical Characteristics
T
A
= 25°C unless otherwise noted
Symbol
Off Characteristics
BV
DSS
∆
BV
DSS
∆
T
J
I
DSS
I
GSS
V
GS(th)
∆
V
GS(th)
∆
T
J
R
DS(on)
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage
V
GS
= 0 V, I
D
= –250
µ
A
I
D
= –250
µ
A, Referenced to 25
°
C
V
DS
= –24 V, V
GS
= 0 V
V
GS
=
±
25 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= –250
µ
A
I
D
= –250
µ
A, Referenced to 25
°
C
V
GS
= –10 V, I
D
= –1.3 A
V
GS
= –4.5 V, I
D
= –1.1 A
V
GS
= –4.5 V, I
D
= –1.1 A, T
J
= 125
°
C
V
DS
= –5 V, I
D
= –0.9 A
V
DS
= –15 V, V
GS
= 0 V, f = 1.0 MHz
–0.8
–2.0
4
150
250
330
2.0
180
300
400
–30
–17
–1
±
100
–2.5
V
mV/
°
C
µ
A
nA
Parameter
Test Conditions
Min
Typ
Max Units
On Characteristics
(Note 2)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
Forward Transconductance
V
mV/
°
C
m
Ω
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
I
S
V
SD
t
rr
Q
rr
S
Dynamic Characteristics
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
150
40
20
pF
pF
pF
Switching Characteristics
(Note 2)
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
V
DS
= –10V, I
D
= –0.9 A,
V
GS
= –4.5 V
V
DD
= –10 V, I
D
= –1 A,
V
GS
= –10 V, R
GEN
= 6
Ω
4
15
10
1
1.4
0.5
0.5
8
28
18
2
1.9
ns
ns
ns
ns
nC
nC
nC
Drain–Source Diode Characteristics and Maximum Ratings
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward Voltage
Diode Reverse Recovery Time
Diode Reverse Recovery Charge
V
GS
= 0 V, I
S
= –0.42 A
I
F
= –3.9 A,
dI
F
/dt = 100 A/µs
(Note 2)
–0.8
17
7
–0.42
–1.2
A
V
ns
nC
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting
surface of the drain pins R
θ
JC
is guaranteed by design while R
θ
JA
is determined by the user’s board design.
(a) R
θ
JA
= 250°C/W when mounted on a 0.02 in
2
pad of 2oz. copper.
(b) R
θ
JA
= 270°C/W when mounted on a 0.001 in
2
pad of 2oz. copper.
2. Pulse Test: Pulse Width < 300
µ
s, Duty Cycle < 2.0%
2
FDN352AP Rev. C1
www.fairchildsemi.com
FDN352AP Single P-Channel, PowerTrench
®
MOSFET
Typical Characteristics
10
V
GS
= -10V
8
2.4
V
GS
= -4.0V
2.2
2.0
-4.5V
1.8
-5.0V
1.6
-6.0V
1.4
1.2
1.0
0.8
0
1
2
3
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
4
5
0
2
4
6
-I
D
, DRAIN CURRENT (A)
8
10
-7.0V
-8.0V
-10V
-6.0V
6
-4.5V
4
-4.0V
2
-3.5V
-3.0V
0
Figure 1. On-Region Characteristics.
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
0.7
-I
D
, DRAIN CURRENT (A)
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.4
R
DS(ON)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
1.2
R
DS(ON)
, ON-RESISTANCE (OHM)
I
D
= -0.9A
V
GS
= -10V
I
D
= -0.45A
0.6
0.5
1
0.4
T
A
= 125
o
C
0.3
T
A
= 25
o
C
0.2
0.8
0.6
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (
o
C)
125
150
0.1
2
4
6
8
-V
GS
, GATE TO SOURCE VOLTAGE (V)
10
Figure 3. On-Resistance Variation with
Temperature.
10
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
100
-I
S
, REVERSE DRAIN CURRENT (A)
V
DS
= -5V
V
GS
= 0V
-I
D
, DRAIN CURRENT (A)
8
T
A
= -55
o
C
125
o
C
10
1
0.1
25
o
C
6
25 C
o
T
A
= 125
o
C
4
0.01
0.001
0.0001
-55
o
C
2
0
1
2
3
4
5
6
-V
GS
, GATE TO SOURCE VOLTAGE (V)
7
8
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
3
FDN352AP Rev. C1
www.fairchildsemi.com
FDN352AP Single P-Channel, PowerTrench
®
MOSFET
Typical Characteristics
10
I
D
= -0.9A
200
f = 1 MHz
V
GS
= 0 V
V
DS
= -10V
-20V
6
-15V
4
150
-V
GS
, GATE-SOURCE VOLTAGE (V)
8
CAPACITANCE (pF)
C
iss
100
C
oss
50
C
rss
2
0
0
0.5
1
1.5
2
Q
g
, GATE CHARGE (nC)
2.5
3
0
0
5
10
15
20
25
30
-V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
100
50
Figure 8. Capacitance Characteristics.
P(pk), PEAK TRANSIENT POWER (W)
40
-I
D
, DRAIN CURRENT (A)
10
R
DS(ON)
LIMIT
1ms
1
10ms
100ms
1s
0.1
V
GS
= -10V
SINGLE PULSE
R
θ
JA
= 270
o
C/W
T
A
= 25
o
C
0.01
0.1
1
10
-V
DS
, DRAIN-SOURCE VOLTAGE (V)
10s
DC
100µs
SINGLE PULSE
R
θ
JA
= 270°C/W
T
A
= 25°C
30
20
10
100
0
0.0001
0.001
0.01
0.1
1
t
1
, TIME (sec)
10
100
1000
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
D = 0.5
0.2
R
θ
JA
(t) = r(t) * R
θ
JA
R
θ
JA
= 270°C/W
P(pk)
t
1
t
2
T
J
– T
A
= P * R
θ
JA
(t)
Duty Cycle, D = t
1
/ t
2
0.1
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
0.001
0.0001
0.001
0.01
0.1
t
1
, TIME (sec)
1
10
100
1000
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
4
FDN352AP Rev. C1
www.fairchildsemi.com
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