IDT72V265LA20TF8 datasheet, PDF

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IDT72V265LA20TF8: DescriptionFIFO, 16KX18, 12ns, Synchronous, CMOS, PQFP64, SLIM, TQFP-64; Categorystorage; File Size433KB，27 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT72V265LA20TF8 Overview

FIFO, 16KX18, 12ns, Synchronous, CMOS, PQFP64, SLIM, TQFP-64

IDT72V265LA20TF8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	SLIM, TQFP-64
Contacts	64
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	12 ns
Other features	RETRANSMIT
Maximum clock frequency (fCLK)	50 MHz
period time	20 ns
JESD-30 code	S-PQFP-G64
JESD-609 code	e0
length	10 mm
memory density	294912 bit
Memory IC Type	OTHER FIFO
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	64
word count	16384 words
character code	16000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16KX18
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP64,.47SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.015 A
Maximum slew rate	0.05 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	10 mm
Base Number Matches	1

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3.3 VOLT CMOS SuperSync FIFO™

8,192 x 18

16,384 x 18

FEATURES:

•

IDT72V255LA

IDT72V265LA

•

Choose among the following memory organizations:

IDT72V255LA

8,192 x 18

IDT72V265LA

16,384 x 18

Pin-compatible with the IDT72V275/72V285 and IDT72V295/

72V2105 SuperSync FIFOs

Functionally compatible with the 5 Volt IDT72255/72265 family

10ns read/write cycle time (6.5ns access time)

Fixed, low first word data latency time

5V input tolerant

Auto power down minimizes standby power consumption

Master Reset clears entire FIFO

Partial Reset clears data, but retains programmable settings

Retransmit operation with fixed, low first word data

latency time

Empty, Full and Half-Full flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags, each flag

can default to one of two preselected offsets

Program partial flags by either serial or parallel means

Select IDT Standard timing (using

and

flags) or First

Word Fall Through timing (using

and

flags)

Output enable puts data outputs into high impedance state

Easily expandable in depth and width

Independent Read and Write clocks (permit reading and

writing simultaneously)

Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-

pin Slim Thin Quad Flat Pack (STQFP)

High-performance submicron CMOS technology

Industrial temperature range (–40°C to +85°C) is available

DESCRIPTION:

The IDT72V255LA/72V265LA are functionally compatible versions of the

IDT72255/72265 designed to run off a 3.3V supply for very low power

consumption. The IDT72V255LA/72V265LA are exceptionally deep, high

speed, CMOS First-In-First-Out (FIFO) memories with clocked read and

write controls. These FIFOs offer numerous improvements over previous

SuperSync FIFOs, including the following:

•

The limitation of the frequency of one clock input with respect to the other

has been removed. The Frequency Select pin (FS) has been removed,

thus it is no longer necessary to select which of the two clock inputs, RCLK

or WCLK, is running at the higher frequency.

FUNCTIONAL BLOCK DIAGRAM

WEN

WCLK

-D

LD SEN

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

EF/OR

PAE

FWFT/SI

WRITE CONTROL

LOGIC

RAM ARRAY

8,192 x 18

16,384 x 18

FLAG

LOGIC

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

-Q

4672 drw 01

The IDT logo is a registered trademark and the SuperSyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2001 Integrated Device Technology, Inc

APRIL 2001

DSC-4672/1

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