ZL50415/GKC datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Telecom circuit> ZL50415/GKC

ZL50415/GKC: DescriptionLAN Switching Circuit, PBGA553, 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553; CategoryTelecom circuit; File Size562KB，96 Pages; ManufacturerCONEXANT; Websitehttp://www.conexant.com/

Download Datasheet Parametric Compare View All

ZL50415/GKC Overview

LAN Switching Circuit, PBGA553, 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553

ZL50415/GKC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	CONEXANT
Parts packaging code	BGA
package instruction	HBGA, BGA553,29X29,50
Contacts	553
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B553
length	37.5 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	553
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	HBGA
Encapsulate equivalent code	BGA553,29X29,50
Package shape	SQUARE
Package form	GRID ARRAY, HEAT SINK/SLUG
Peak Reflow Temperature (Celsius)	225
power supply	2.5,3.3 V
Certification status	Not Qualified
Maximum seat height	2.46 mm
Nominal supply voltage	2.5 V
surface mount	YES
Telecom integrated circuit types	LAN SWITCHING CIRCUIT
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	37.5 mm
Base Number Matches	1

Preview

Download Datasheet

View All

ZL50415

Unmanaged 16-Port 10/100M Layer-2

Ethernet Switch

Data Sheet

Features

•

Integrated Single-Chip 10/100M Ethernet Switch

• Sixteen 10/100 Mbps auto-negotiating Fast Ethernet

(FE) ports with RMII or GPSI (7WS) interface

options per port

April 2006

Ordering Information

ZL50415/GKC

ZL50415GKG2

553 Pin HSBGA

553 Pin HSBGA**

•

Supports one Frame Data Buffer (FDB) memory

domains

(1 MB or 2 MB)

with pipelined, sync-burst

SRAM at 100 MHz

• Applies centralized shared memory architecture

**Pb Free Tin/Silver/Copper

-40°C to 85°C

with 2 drop precedence levels

• Scheduling using delay bounded (DB), strict priority

(SP), and Weighted Fair Queuing (WFQ) disciplines

• User controlled WRED thresholds

• Buffer management: per-class, shared, and per-port

buffer reservations

•

L2 Switching

• MAC address self learning, up to 64K MAC

addresses

• Supports port-based VLAN

•

High performance packet classification and

switching at full-wire speed

CPU access supports the following interface

options:

• Serial interface in unmanaged mode, with optional

C EEPROM support

•

Classification based on:

• Port-based priority: priority in a frame can be

overwritten by the priority of port

• VLAN Priority field in VLAN tagged frame (IEEE

802.1p)

• DS/TOS field in IP packet

• UDP/TCP logical ports: 8 hard-wired and 8

programmable ports, including one programmable

range

•

Supports Ethernet multicasting and broadcasting

and flooding control

Supports per-system option to enable flow

control for best effort frames even on QoS-

enabled ports

QoS Support

• 4 transmission priorities for Fast Ethernet ports

• Per-queue weighted random early discard (WRED)

VLAN 1 MCT

•

The drop precedence of the above classifications

is programmable

Supports IEEE 802.3ad link aggregation

•

port trunking groups

Frame Data Buffer A

SRAM (1 M / 2 M)

FDB Interface

LED

FCB

Frame Engine

Engine

MCT

Link

16 x 10/100M

RMII

Ports 0 - 15

Management

Module

Serial

Figure 1 - System Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ZL50415

Description

Data Sheet

The ZL50415 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip

provides 16 ports at 10/100 Mbps and a CPU interface for unmanaged switch applications.

The chip supports up to 64K MAC addresses and port-based Virtual LANs (VLANs). The centralized shared

memory architecture permits a very high performance packet forwarding rate at full wire speed. The chip is

optimized to provide low-cost, high-performance workgroup switching.

A Frame Buffer Memory domain utilizes cost-effective, high-performance synchronous SRAM with aggregate

bandwidth of 6.4 Gbps to support full wire speed on all ports simultaneously.

With delay bounded, strict priority, and/or WFQ transmission scheduling and WRED dropping schemes, the

ZL50415 provides powerful QoS functions for various multimedia and mission-critical applications. The chip

provides 4 transmission priorities and 2 levels of dropping precedence. Each packet is assigned a transmission

priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or

the UDP/TCP logical port fields in IP packets. The ZL50415 recognizes a total of 16 UDP/TCP logical ports, 8 hard-

wired and 8 programmable (including one programmable range).

The ZL50415 supports 2 groups of port trunking/load sharing. Two groups are dedicated to 10/100 ports, where

each 10/100 group can contain up to 4 ports. Port trunking/load sharing can be used to group ports between

interlinked switches to increase the effective network bandwidth.

In half-duplex mode all ports support backpressure flow control to minimize the risk of losing data during long

activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50415 also supports a per-system

option to enable flow control for best effort frames, even on QoS-enabled ports.

The ZL50415 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are

capable of directly interfacing to LVTTL levels. The ZL50415 is packaged in a 553-pin Ball Grid Array package.

Zarlink Semiconductor Inc.

ZL50415

Data Sheet

Table of Contents

1.0 BGA and Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1 BGA Views (Top-View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1.1 Encapsulated view in unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.2 Ball – Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3 Ball – Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.4 Signal Mapping and Internal Pull Up/Down Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.0 Block Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.1 Frame Data Buffer (FDB) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.2 MAC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.2.1 RMII MAC Module (RMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.2.1.1 GPSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.2.1.2 SCANLINK and SCANCOL interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.2.2 PHY Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.3 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.4 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.5 LED Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.5.1 Port Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.5.2 LED Interface Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.6 Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.7 Timeout Reset Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.0 System Configuration (Stand-alone and Stacking) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1 Management and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1.1 I2C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.1.1.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.1.1.2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.1.1.3 Data Direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.1.1.4 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.1.1.5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.1.1.6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.1.2 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.1.2.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.1.2.2 Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.0 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1 Unicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2 Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.0 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.2 Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.3.1 MAC Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.4 Port--Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.5 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.5.1 Priority Classification Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.0 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1 Data Forwarding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Zarlink Semiconductor Inc.

ZL50415/GKC Related Products

	ZL50415/GKC	ZL50415GKG2
Description	LAN Switching Circuit, PBGA553, 37.50 X 37.50 MM, 2.33 MM HEIGHT, MS-034, HSBGA-553	LAN Switching Circuit, PBGA553, 37.50 X 37.50 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, HSBGA-553
Maker	CONEXANT	CONEXANT
Parts packaging code	BGA	BGA
package instruction	HBGA, BGA553,29X29,50	HBGA,
Contacts	553	553
Reach Compliance Code	compliant	compli
JESD-30 code	S-PBGA-B553	S-PBGA-B553
length	37.5 mm	37.5 mm
Humidity sensitivity level	1	1
Number of functions	1	1
Number of terminals	553	553
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HBGA	HBGA
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY, HEAT SINK/SLUG	GRID ARRAY, HEAT SINK/SLUG
Peak Reflow Temperature (Celsius)	225	260
Certification status	Not Qualified	Not Qualified
Maximum seat height	2.46 mm	2.46 mm
Nominal supply voltage	2.5 V	2.5 V
surface mount	YES	YES
Telecom integrated circuit types	LAN SWITCHING CIRCUIT	LAN SWITCHING CIRCUIT
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	30
width	37.5 mm	37.5 mm

Recommended Resources

TLG4 type thyristor automatic excitation device circuit

Use P228 to make infrared remote control energy-saving lighting lamps

Music doorbell circuit with flashing light

frequency modulation generator circuit

0.6-1.5V/2-6A voltage stabilizing circuit

875p computer motherboard circuit diagram_006

Popular driver for LoRa module, hehe: Recently, I was debugging the SX1278 wireless module for wireless temperature control solutions, and I would like to recommend a good driver to my friends. Welcome all technical experts to discuss the...; keng123 RF/Wirelessly

30 pieces of advice from the commentator of "Win in China" for young people born in the 1980s: 1. If a young man has no ideas for three years, his life will basically be like this, without much change. 2. Successful people are courageous and determined. I once heard someone talk about the succe...; 心仪 Talking about work

AD09 has problems loading libraries: When I open the schematic and click on libraries, a problem occurs. The files cannot be loaded. All the files in the box are red and cannot be deleted. Please solve it. [img]https://gss0.baidu.com/9vo...; y2018y PCB Design

Altera SoC Experience Tour + Received Board: I received the board today. The packaging is very solid and the accessories are very complete. Here are two pictures.Now I see that the significant feature of Altera development is that it has its own...; flower_huanghua FPGA/CPLD

Use buttons and digital tubes to make a dynamic display: How can I make the number on the digital tube move to the right every time I press a key? For example, if I press 1 first, then 5, the digital tube displays 51, and so on. What is the code?...; Dele_chen 51mcu

Oil price increase, wages?: Title: 1900 yuan/month urgently hiring part-time (suitable for part-time students) The company is a professional outsourcing company that provides typing, typesetting and proofreading services for dom...; xunmengtaxiang Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components