72V3694L10PFG8 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > storage> 72V3694L10PFG8

72V3694L10PFG8: DescriptionTQFP-128, Reel; Categorystorage; File Size420KB，36 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

Download Datasheet Parametric Compare View All

72V3694L10PFG8 Overview

TQFP-128, Reel

72V3694L10PFG8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TQFP
package instruction	LFQFP, QFP128,.63X.87,20
Contacts	128
Manufacturer packaging code	PKG128
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	6.5 ns
Other features	MAILBOX BYPASS REGISTER
Maximum clock frequency (fCLK)	100 MHz
period time	10 ns
JESD-30 code	R-PQFP-G128
JESD-609 code	e3
length	20 mm
memory density	1179648 bit
Memory IC Type	BI-DIRECTIONAL FIFO
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	128
word count	32768 words
character code	32000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX36
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP128,.63X.87,20
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.005 A
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

Preview

Download Datasheet

View All

3.3 VOLT CMOS SyncBiFIFO

WITH BUS-MATCHING

16,384 x 36 x 2

IDT72V3684

32,768 x 36 x 2

IDT72V3694

65,536 x 36 x 2

IDT72V36104

FEATURES

•

Memory storage capacity:

IDT72V3684 – 16,384 x 36 x 2

IDT72V3694 – 32,768 x 36 x 2

IDT72V36104 – 65,536 x 36 x 2

Clock frequencies up to 100 MHz (6.5ns access time)

Two independent clocked FIFOs buffering data in opposite

directions

Select IDT Standard timing (using

EFA, EFB, FFA,

and

FFB

flags

functions) or First Word Fall Through Timing (using ORA, ORB,

IRA, and IRB flag functions)

Programmable Almost-Empty and Almost-Full flags; each has five

default offsets (8, 16, 64, 256 and 1,024 )

Serial or parallel programming of partial flags

Retransmit Capability

•

Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits

(byte)

Big- or Little-Endian format for word and byte bus sizes

Master Reset clears data and configures FIFO, Partial Reset

clears data but retains configuration settings

Mailbox bypass registers for each FIFO

Free-running CLKA and CLKB may be asynchronous or coincident

(simultaneous reading and writing of data on a single clock edge

is permitted)

Auto power down minimizes power dissipation

Available in space saving 128-pin Thin Quad Flatpack (TQFP)

Pin compatible to the lower density parts, IDT72V3624/72V3634/

72V3644/72V3654/72V3664/72V3674

Industrial temperature range (–40°C to +85°C) is available

FUNCTIONAL BLOCK DIAGRAM

MBF1

Mail 1

Output Bus-

Matching

Input

RAM ARRAY

16,384 x 36

32,768 x 36

65,536 x 36

Output

CLKA

CSA

W/RA

ENA

MBA

MRS1

PRS1

Port-A

Control

Logic

FIFO1,

Mail1

Reset

Logic

Write

Pointer

Read

Pointer

Status Flag

Logic

EFB/ORB

AEB

FFA/IRA

AFA

FS2

FS0/SD

FS1/SEN

-A

EFA/ORA

AEA

FIFO1

Programmable Flag

Offset Registers

FIFO2

Timing

Mode

FWFT

-B

Status Flag

Logic

Read

Pointer

Write

Pointer

FFB/IRB

AFB

RT1

RTM

RT2

Output

Input Bus-

Matching

16,384 x 36

32,768 x 36

65,536 x 36

Mail 2

Input

FIFO1 and

FIFO2

Retransmit

Logic

RAM ARRAY

FIFO2,

Mail2

Reset

Logic

MRS2

PRS2

Port-B

Control

Logic

4677 drw01

MBF2

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.

CLKB

CSB

W/RB

ENB

MBB

SIZE

COMMERCIAL TEMPERATURE RANGE



2003

NOVEMBER 2003

DSC-4677/5

IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO

WITH

BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS (CONTINUED)

Symbol

FS0/SD

Name

I/O

Description

Flag Offset Select 0/ I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master

Serial Data

Reset, FS1/SEN and FS0/SD, together with FS2, select the flag offset programming method. Three offset

1,024), parallel load from Port A, and serial load.

FS1/SEN Flag Offset Select 1/ I

Serial Enable,

When serial load is selected for flag offset register programming, FS1/SEN is used as an enable

synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load

(1)

FS2

Flag Offset Select 2

I the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the offset

registers is 56 for the IDT72V3684, 60 for the IDT72V3694, and 64 for the IDT72V36104. The first bit write

stores the Y- register (Y1) MSB and the last bit write stores the X-register (X2) LSB.

MBA

Port A Mailbox

I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35

Select

outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level

selects FIFO2 output register data for output.

MBB

Port B Mailbox

Select

Mail1 Register

Flag

Mail2 Register

Flag

FIFO1 Master

Reset

A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35

outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level

selects FIFO1 output register data for output.

MBF1

is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1

MBF1

is LOW.

MBF1

is set HIGH by a LOW-to-HIGH transition of CLKB when a

Port B read is selected and MBB is HIGH.

MBF1

is set HIGH following either a Master or Partial Reset of FIFO1.

MBF2

is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2

MBF2

is LOW.

MBF2

is set HIGH by a LOW-to-HIGH transition of CLKA when a Port

A read is selected and MBA is HIGH.

MBF2

is set HIGH following either a Master or Partial Reset of FIFO2.

A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port

B output register to all zeroes. A LOW-to-HIGH transition on

MRS1

selects the programming method (serial or parallel)

and one of five programmable flag default offsets for FIFO1 and FIFO2. It also configures Port B for bus size and

endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must

occur while

MRS1

is LOW.

A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A

output register to all zeroes. A LOW-to-HIGH transition on

MRS2,

toggled simultaneously with

MRS1,

selects the

programming method (serial or parallel) and one of the programmable flag default offsets for FIFO2. Four LOW-to-

HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while

MRS2

is LOW.

This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin.

If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes the FIFO1 read

and write pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset,

the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable

flag settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO1 read

pointer only to the first memory location.

This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin.

If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes the FIFO2 read

and write selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag

settings are all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO2 read pointer

only to the first memory location.

This pin is used in conjunction with the

RT1

and

RT2

pins. When RTM is HIGH a Retransmit is performed on

FIFO1 or FIFO2 respectively.

A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH

selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port

B. The level of SIZE must be static throughout device operation

A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH

transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.

A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH

transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when

W/RB

is LOW.

MBF1

MBF2

MRS1

MRS2

FIFO2 Master

Reset

PRS1/

RT1

Partial Reset/

Retransmit FIFO1

PRS2/

RT2

Partial Reset/

Retransmit FIFO2

RTM

SIZE

(1)

Retransmit Mode

Bus Size Select

W/RA

W/RB

Port-A Write/

Read Select

Port-B Write/

Read Select

NOTE:

1. FS2, BM and SIZE inputs are not TTL compatible. These inputs should be tied to GND or V

72V3694L10PFG8 Related Products

	72V3694L10PFG8	72V3694L15PFG8	IDT72V36104L10PFG8	72V3694L10PF9	72V3694L15PF9	IDT72V36104L15PFG8	IDT72V3684L15PFG8
Description	TQFP-128, Reel	TQFP-128, Reel	FIFO, 64KX36, 6.5ns, Synchronous, CMOS, PQFP128, TQFP-128	TQFP-128, Tray	TQFP-128, Tray	FIFO, 64KX36, 10ns, Synchronous, CMOS, PQFP128, TQFP-128	FIFO, 16KX36, 10ns, Synchronous, CMOS, PQFP128, TQFP-128
Is it lead-free?	Lead free	Lead free	Lead free	Contains lead	Contains lead	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	incompatible	incompatible	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TQFP	TQFP	QFP	TQFP	TQFP	QFP	QFP
package instruction	LFQFP, QFP128,.63X.87,20	GREEN, TQFP-128	TQFP-128	LFQFP,	LFQFP,	TQFP-128	LFQFP,
Contacts	128	128	128	128	128	128	128
Reach Compliance Code	unknown	compliant	compliant	not_compliant	not_compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Maximum access time	6.5 ns	10 ns	6.5 ns	6.5 ns	10 ns	10 ns	10 ns
Other features	MAILBOX BYPASS REGISTER	MAILBOX BYPASS REGISTER	MAILBOX BYPASS REGISTER	MAILBOX BYPASS REGISTER	MAILBOX BYPASS REGISTER	MAILBOX BYPASS REGISTER	MAILBOX BYPASS REGISTER
period time	10 ns	15 ns	10 ns	10 ns	15 ns	15 ns	15 ns
JESD-30 code	R-PQFP-G128	R-PQFP-G128	R-PQFP-G128	R-PQFP-G128	R-PQFP-G128	R-PQFP-G128	R-PQFP-G128
JESD-609 code	e3	e3	e3	e0	e0	e3	e3
length	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm	20 mm
memory density	1179648 bit	1179648 bit	2359296 bit	1179648 bit	1179648 bit	2359296 bit	589824 bit
memory width	36	36	36	36	36	36	36
Humidity sensitivity level	3	3	3	3	3	3	3
Number of functions	1	1	1	1	1	1	1
Number of terminals	128	128	128	128	128	128	128
word count	32768 words	32768 words	65536 words	32768 words	32768 words	65536 words	16384 words
character code	32000	32000	64000	32000	32000	64000	16000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	32KX36	32KX36	64KX36	32KX36	32KX36	64KX36	16KX36
Exportable	YES	YES	YES	YES	YES	YES	YES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	260	225	225	260	260
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V
Minimum supply voltage (Vsup)	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed	MATTE TIN	MATTE TIN	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	MATTE TIN	MATTE TIN
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	NOT SPECIFIED	30	NOT SPECIFIED	NOT SPECIFIED	30	30
width	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm
Brand Name	Integrated Device Technology	Integrated Device Technology	-	Integrated Device Technology	Integrated Device Technology	-	-
Manufacturer packaging code	PKG128	PKG128	-	PK128	PK128	-	-
Certification status	Not Qualified	-	Not Qualified	-	-	Not Qualified	Not Qualified
Base Number Matches	1	1	1	1	1	-	-

Recommended Resources

Analysis of development prospects of power sensors

Improved single-shot timing circuit composed of 2 PUT lamps

Level indicator circuit

Fluorescent lamp electronic ballast circuit

Photoelectric isolation circuit used as scanner

Computer motherboard circuit diagram 815 2_03

Is AD9854ASQ a good buy?: [i=s]This post was last edited by paulhyde on 2014-9-15 03:30[/i] Many Taobao stores are out of stock...; longhaozheng Electronics Design Contest

EEWORLD University ---- Fluke high-end infrared thermal imager application case: opening up unlimited infrared applications: Fluke high-end infrared thermal imager application case: Open unlimited infrared applications : https://training.eeworld.com.cn/course/623...; chenyy Test/Measurement

[Questions and Answers on Component Purchase, Lucky Gain] Part 3 - What should I do if the components I purchased are not in the same package as the PCB?: Last issue of [E-questions and answers on device purchase, lucky grabbing] 2 - When developing, a small number of devices are needed. Will you choose to apply for samples? https://bbs.eeworld.com.cn/t...; EEWORLD社区 Buy&Sell

18 billion kilometers! How does Voyager transmit data to Earth?: The National Aeronautics and Space Administration (NASA) announced at the 2018 Geophysical Meeting in the United States that by comparing the data sent back by different instruments on Voyager 2, afte...; btty038 RF/Wirelessly

Register for the Zurich Instruments seminar and win a Swiss Army Knife!: On September 17 (Thursday) at 2:00 p.m., Zurich Instruments will hold an online seminar "Impedance Analyzer from Switzerland" through Tencent Conference. The meeting will last about 1 hour.This webina...; eric_wang Sensor

Self-designed large-size digital tube drive circuit: I designed a 5-inch digital tube drive circuit for dynamic scanning. Please refer to it and give me some advice. The digital tube brightness of the circuit I designed before was not enough. This time ...; 山川子俊 Microchip MCU

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components