Features
•
AVR
®
– High-performance and Low-power RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
Data and Nonvolatile Program Memories
– 8K Bytes of In-System Programmable Flash
SPI Serial Interface for In-System Programming
Endurance: 1,000 Write/Erase Cycles
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Programming Lock for Software Security
Peripheral Features
– 8-channel, 10-bit ADC
– Programmable UART
– Master/Slave SPI Serial Interface
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare and
Capture Modes and Dual 8-, 9-, or 10-bit PWM
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset Circuit
– Real-time Clock (RTC) with Separate Oscillator and Counter Mode
– External and Internal Interrupt Sources
– Three Sleep Modes: Idle, Power Save and Power-down
Power Consumption at 4 MHz, 3V, 20°C
– Active: 6.4 mA
– Idle Mode: 1.9 mA
– Power-down Mode: <1 µA
I/O and Packages
– 32 Programmable I/O Lines
– 40-lead PDIP, 44-lead PLCC, 44-lead TQFP, and 44-pad MLF
Operating Voltages
– V
CC
: 4.0 - 6.0V AT90S8535
– V
CC
: 2.7 - 6.0V AT90LS8535
Speed Grades:
– 0 - 8 MHz for the AT90S8535
– 0 - 4 MHz for the AT90LS8535
•
•
•
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT90S8535
AT90LS8535
•
•
•
•
Rev. 1041H–11/01
1
Pin Configurations
2
AT90S/LS8535
1041H–11/01
AT90S/LS8535
Description
The AT90S8535 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90S8535
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
Figure 1.
The AT90S8535 Block Diagram
PA0 - PA7
PC0 - PC7
Block Diagram
VCC
PORTA DRIVERS
PORTC DRIVERS
GND
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
DATA REGISTER
PORTC
DATA DIR.
REG. PORTC
8-BIT DATA BUS
AVCC
ANALOG MUX
AGND
AREF
ADC
OSCILLATOR
XTAL1
INTERNAL
OSCILLATOR
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
XTAL2
RESET
PROGRAM
FLASH
SRAM
MCU CONTROL
REGISTER
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
X
Y
Z
TIMER/
COUNTERS
INSTRUCTION
DECODER
INTERRUPT
UNIT
CONTROL
LINES
ALU
EEPROM
STATUS
REGISTER
PROGRAMMING
LOGIC
SPI
UART
ANALOG
COMPARATOR
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
+
-
PORTB DRIVERS
PORTD DRIVERS
PB0 - PB7
PD0 - PD7
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1041H–11/01
The AVR core combines a rich instruction set with 32 general-purpose working regis-
ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in
one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
The AT90S8535 provides the following features: 8K bytes of In-System Programmable
Flash, 512 bytes EEPROM, 512 bytes SRAM, 32 general-purpose I/O lines, 32 general-
purpose working registers, Real-time Clock (RTC), three flexible timer/counters with
compare modes, internal and external interrupts, a programmable serial UART, 8-chan-
nel, 10-bit ADC, programmable Watchdog Timer with internal oscillator, an SPI serial
port and three software-selectable power-saving modes. The Idle Mode stops the CPU
while allowing the SRAM, timer/counters, SPI port and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the oscilla-
tor, disabling all other chip functions until the next interrupt or hardware reset. In Power
Save Mode, the timer oscillator continues to run, allowing the user to maintain a timer
base while the rest of the device is sleeping.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
through an SPI serial interface or by a conventional nonvolatile memory programmer.
By combining an 8-bit RISC CPU with In-System Programmable Flash on a monolithic
chip, the Atmel AT90S8535 is a powerful microcontroller that provides a highly flexible
and cost effective solution to many embedded control applications.
The AT90S8535 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit
emulators and evaluation kits.
Pin Descriptions
VCC
GND
Port A (PA7..PA0)
Digital supply voltage.
Digital ground.
Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors
(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED dis-
plays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,
they will source current if the internal pull-up resistors are activated.
Port A also serves as the analog inputs to the A/D Converter.
The Port A pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output
buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. Port B also serves the functions of various
special features of the AT90S8535 as listed on page 78.
The Port B pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output
buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source
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AT90S/LS8535
1041H–11/01
AT90S/LS8535
current if the pull-up resistors are activated. Two Port C pins can alternatively be used
as oscillator for Timer/Counter2.
The Port C pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output
buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port D also serves the functions of various special features of the AT90S8535 as listed
on page 86.
The Port D pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting oscillator amplifier.
AVCC is the supply voltage pin for Port A and the A/D Converter. If the ADC is not used,
this pin must be connected to VCC. If the ADC is used, this pin must be connected to
VCC via a low-pass filter. See page 68 for details on operation of the ADC.
AREF is the analog reference input for the A/D Converter. For ADC operations, a volt-
age in the range 2V to AV
CC
must be applied to this pin.
Analog ground. If the board has a separate analog ground plane, this pin should be con-
nected to this ground plane. Otherwise, connect to GND.
XTAL1
XTAL2
AVCC
AREF
AGND
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1041H–11/01
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