530PA60M0000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > oscillator> 530PA60M0000DG

530PA60M0000DG: DescriptionCMOS Output Clock Oscillator, 60MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; Categoryoscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530PA60M0000DG Overview

CMOS Output Clock Oscillator, 60MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530PA60M0000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Is Samacsys	N
Other features	TRAY
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	60 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS
physical size	7.0mm x 5.0mm x 1.85mm
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Memory system reset circuit (TLC7XX)

Rotor, stator and drive circuit of brushless motora

Microvolt detector.gif

Single supply function generator

Sine wave-rectangular wave oscillator

Leakage indication circuit

430f5529 Help me ah ah ah: I am participating in an electrical competition and need to learn msp430f5529. The teacher requires us to use the microcontroller to display voltage and current. How can I do this? Please help me....; 柯景腾 Microcontroller MCU

Received a gift from the lecture hall: I received a gift today for a lecture. Here’s a picture to show it off.Let's take a group photo firstIt includes a wireless mouse and a wireless presenter for PPT. The wireless presenter should use in...; wstt Microcontroller MCU

PB5.0 error when exporting SDK: An error occurred when exporting SDK from PB5.0. Please help me. When exporting SDK from PB5.0, the following error occurred. Can an expert give me a pulse and see where the problem lies? I have just ...; zuigui111 Embedded System

Zigbee protocol stack learning serial port transparent transmission experiment (SerialApp) process analysis: The first function: networking of the coordinator, terminal devices and routing devices discovering the network and joining the network //Step 1: Z-Stack starts with the main() function. The main() fu...; wateras1 RF/Wirelessly

EEWORLD University ---- Power supply design tips 1: Choose the correct operating frequency for your power supply: Power Design Tip 1: Choose the right operating frequency for your power supply : https://training.eeworld.com.cn/course/504...; dongcuipin Power technology

STM32 FSMC connected to LCD routine: How does MCU determine the register address of the external LCD controller?: Keil4's built-in demo: STM32F103VE uses FSMC to drive LCD AM-240320L8TNQW00H (ILI9320), MCU's A0 is connected to LCD's RS, and in lcd.c there is: typedef struct { __IO uint16_t LCD_REG; __IO uint16_t ...; illino stm32/stm8

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components