Changes to Ordering Guide .......................................................... 42
11/04—Rev. 0 to Rev. A
Changes to Absolute Maximum Ratings .......................................6
Changes to Figure 4 ...........................................................................7
Changes to Table 4.............................................................................7
Changes to Grounding and Layout section ................................ 32
Changes to Figure 42...................................................................... 32
Changes to Ordering Guide .......................................................... 43
7/04—Revision 0: Initial Version
Rev. E | Page 2 of 45
Data Sheet
SPECIFICATIONS
V
CC
= 2.7 V to 3.6 V, V
REF
= 2.5 V internal or external, f
DCLK
= 2 MHz, T
A
= −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
DC ACCURACY
Resolution
No Missing Codes
Integral Nonlinearity (INL)
1
Differential Nonlinearity (DNL)
1
Negative DNL
Positive DNL
Offset Error
1
Gain Error
1
Noise
Power Supply Rejection
Internal Clock Frequency
SWITCH DRIVERS
On Resistance
1
Y+, X+
Y−, X−
ANALOG INPUTS
Input Voltage Ranges
DC Leakage Current
Input Capacitance
Accuracy
REFERENCE INPUT/OUTPUT
Internal Reference Voltage
Internal Reference Tempco
V
REF
Input Voltage Range
DC Leakage Current
V
REF
Input Impedance
TEMPERATURE MEASUREMENT
Temperature Range
Resolution
Differential Method
2
Single Conversion Method
3
Accuracy
Differential Method
2
Single Conversion Method
3
BATTERY MONITOR
Input Voltage Range
Input Impedance
Accuracy
Min
12
11
Typ
Max
Unit
Bits
Bits
LSB
LSB
LSB
LSB
LSB
µV rms
dB
MHz
Test Conditions/Comments
AD7877
12
±2
−0.99
+2
±5
±3
70
70
2
LSB size = 610 µV
Minimum LSB size = 610 µV
Specified for 11bits
Specified for 11 bits; external reference
14
14
0
±0.1
30
0.3
2.44
±50
1
1
V
CC
±1
2.55
V
REF
Ω
Ω
V
µA
pF
%
V
ppm/°C
V
µA
GΩ
All channels, internal V
REF
CS = GND or V
CC
; typically 25 Ω when the on-board
reference is enabled
−40
1.6
0.3
±4
±2
0.5
14
1
+85
°C
°C
°C
°C
°C
0°C to 70°C
Calibrated at 25°C
@ V
REF
= 2.5 V
Sampling, 1 GΩ when the battery monitor is off
External/internal reference, see Figure 26
5
3.2
V
kΩ
%
Rev. E | Page 3 of 45
AD7877
Parameter
DAC
Resolution
Integral Nonlinearity
Differential Nonlinearity
Voltage Mode
Output Voltage Range
Slew Rate
Output Settling Time
Capacitive Load Stability
Output Impedance
Short-Circuit Current
Current Mode
Output Current Range
Output Impedance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN 4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
4
Output Coding
CONVERSION RATE
Conversion Time
Throughput Rate
POWER REQUIREMENTS
V
CC
(Specified Performance)
V
DRIVE
I
CC
Converting Mode
Min
Typ
8
±1
±1
0 − V
CC
/2
0 − V
CC
−0.4, +0.5
12
50
75
21
0
Max
Unit
Bits
Bits
Guaranteed monotonic by design
V
V
V/µs
µs
pF
kΩ
mA
µA
DAC register Bit 2 = 0, Bit 0 = 0
DAC register Bit 2 = 0, Bit 0 = 1
Test Conditions/Comments
Data Sheet
15
100
0 to 3/4 scale, R
LOAD
= 10 kΩ, C
LOAD
= 50 pF
R
LOAD
= 10 kΩ
Power-down mode
1000
Open
DAC register, Bit 2 = 1; full-scale current is set by R
RNG
Power-down mode
0.7 V
DRIVE
0.3
V
DRIVE
±1
10
V
DRIVE
− 0.2
0.4
±10
10
V
V
µA
pF
V
V
µA
pF
Typically 10 nA, V
IN
= 0 V or V
CC
I
SOURCE
= 250 µA, V
CC
/V
DRIVE
= 2.7 V to 5.25 V
I
SINK
= 250 µA
Straight (natural) binary
8
125
2.7
1.65
240
650
900
150
3.6
V
CC
380
900
µs
kSPS
V
V
µA
µA
µA
µA
µA
CS high to DAV low
Functional from 2.2 V to 5.25 V
Digital inputs = 0 V or V
CC
ADC on, internal reference off, V
CC
= 3.6 V
ADC on, internal reference on, V
CC
= 3.6 V
ADC on, internal reference on, DAC on
ADC on, but not converting, internal reference off,
V
CC
= 3.6 V
Static
Shutdown Mode
1
2
1
See the Terminology section.
Difference between Temp0 and Temp1 measurement. No calibration necessary.
3
Temperature drift is −2.1 mV/°C.
4
Sample tested @ 25°C to ensure compliance.
Rev. E | Page 4 of 45
Data Sheet
TIMING SPECIFICATIONS
AD7877
T
A
= T
MIN
to T
MAX
, unless otherwise noted, V
CC
= 2.7 V to 5.25 V, V
REF
= 2.5 V. Sample tested at 25°C to ensure compliance. All input
signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.6 V.
Table 2.
Parameter
f
DCLK 1
t
1
t
2
t
3
t
4
t
5
t
6 2
t
7 2
t
8 3
t
9
1
2
Limit at T
MIN
, T
MAX
10
20
16
20
20
12
12
16
16
16
0
Unit
kHz min
MHz max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
Description
CS falling edge to first DCLK rising edge
DCLK high pulse width
DCLK low pulse width
DIN setup time
DIN hold time
CS falling edge to DOUT, three-state disabled
DCLK falling edge to DOUT valid
CS rising edge to DOUT high impedance
CS rising edge to DCLK ignored
Mark/space ratio for the DCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 2.0 V.
3
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
TIMING DIAGRAMS
CS
t
1
DCLK
1
2
t
2
3
t
3
15
16
t
9
t
5
t
4
DIN
MSB
LSB
DOUT
MSB
LSB
Figure 2. Detailed Timing Diagram
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
03796-003
Figure 3. Load Circuit for Digital Output Timing Specifications
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