AC drive for liquid crystal panel during no signal
(NTSC/PAL)
•
Generates timing signal of external sample-and-
hold circuit
•
AFC circuit supporting static and dynamic
fluctuations
•
Pulse driver for liquid crystal panel driver (12.0V)
Applications
Color liquid crystal viewfinders
Structure
Silicon gate CMOS IC
48 pin LQFP (Plastic)
Absolute Maximum Ratings
(5V system)
(Ta = +25°C, V
SS1
= 0V)
•
Supply voltage
•
Input voltage
•
Output voltage
•
Operating temperature
•
Storage temperature
V
CC
V
I
V
O
Topr
Tstg
–0.3 to +7.0
V
–0.3 to V
DD
+0.3 V
–0.3 to V
DD
+0.3 V
–20 to +75
°C
–55 to +125
°C
Absolute Maximum Ratings
(12V system)
(Ta = +25°C, V
SS3
= 0V)
•
Supply voltage
V
EE
–0.3 to +20.0
V
•
Output voltage
V
O
–0.3 to V
EE
+0.3 V
•
Operating temperature Topr
–20 to +75
°C
•
Storage temperature
Tstg
–55 to +125
°C
Recommended Operating Conditions
(5V system)
•
Supply voltage
V
DD
2.7 to 5.5
V
•
Operating temperature Topr
–20 to +75
°C
Recommended Operating Conditions
(12V system)
•
Supply voltage
V
EE
11.5 to 12.5
V
•
Operating temperature Topr
–20 to +75
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication
or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony
cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94421-TE
CXD2403AR
Block Diagram
CKO
39
Master CK
7
8
9
TST0
TST1
TST2
CKI
40
XCLR
PLNT
SLCK
3
2
6
H-SYNC
Detector
H-SKEW
Detector
PLL Phase Comparator
37
RPD
35
XCLP
36
HD
Half-H
Killer
PLL
Counter
SYNC
27
38
V
DD
1
41
V
SS
1
1
N.C.
V
DD
2
5
25
V
SS
2
13
V
EE
24
V
SS
3
V-SYNC
Separator
(Noise Shape)
N.C.
10
N.C.
11
N.C.
12
N.C.
14
N.C.
15
45
HP1
46
HP2
47
HP3
48
HP4
16
CLR
21
HST
23
HCK1
22
HCK2
31
SH1
32
SH2
N.C.
26
FLDI
28
N.C.
42
N.C.
43
N.C.
44
EN
17
VST
18
VCK1
19
VCK2
20
FLDO
29
VD
30
PAL Pulse
Eliminator
V-Timing
Pulse Generator
H-Timing
Pulse
Generator
33
SH3
Field & Line
Controller
4
SLFR
34
FRP
–2–
CXD2403AR
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
V
DD
2
PLNT
XCLR
SLFR
N.C.
SLCK
TST0
TST1
TST2
N.C.
N.C.
N.C.
V
EE
N.C.
N.C.
CLR
EN
VST
VCK1
VCK2
HST
HCK2
HCK1
V
SS
3
V
SS
2
N.C.
SYNC
FLDI
FLDO
VD
SH1
SH2
SH3
FRP
XCLP
HD
RPD
V
DD
1
CKO
CKI
I/O
I
I
I
I
—
I
I
I
I
—
—
—
I
—
—
O
O
O
O
O
O
O
O
I
I
—
I
I
O
O
O
O
O
O
O
O
O
I
O
I
Description
(H: Pull Up, L: Pull Down)
Input Pin for
Open Status
L
H
L
—
L
L
L
L
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5V system power supply
Switches between PAL (High) and NTSC (Low)
Reset at 0V
Switches between field inversion (High) and line inversion (Low)
No connected
Switches between LCX003/004 (Low) and LCX005 (High)
Test
Test
Test
No connected
No connected
No connected
12V system power supply
No connected
No connected
CLR pulse output (positive polarity)
EN pulse output (negative polarity)
V start pulse output (positive polarity)
V clock pulse 1 output (positive polarity)
V clock pulse 2 output (positive polarity)
H start pulse output (positive polarity)
H clock pulse 2 output (positive polarity)
H clock pulse 1 output (positive polarity)
12V system GND
5V system GND
No connected
Composite sync input (positive polarity)
Field identification signal input ODD (High)/EVEN (Low)
Field identification signal output
VD pulse output (positive polarity)
Sample-and-hold pulse output (positive polarity)
Sample-and-hold pulse output (positive polarity)
Sample-and-hold pulse output (positive polarity)
AC drive timing pulse output
Burst position clamp pulse output (negative polarity)
HD pulse output (positive polarity)
Phase comparator output
5V system power supply
Oscillation cell (output)
Oscillation cell (input)
–3–
CXD2403AR
Pin
No.
41
42
43
44
45
46
47
48
Symbol
V
SS
1
N.C.
N.C.
N.C.
HP1
HP2
HP3
HP4
I/O
I
—
—
—
I
I
I
I
5V system GND
No connected
No connected
Description
Input Pin for
Open Status
—
—
—
H
L
L
H
No connected
Switches for the horizontal display start position
Switches for the horizontal display start position
Switches for the horizontal display start position
Switches for the horizontal display start position
Electrical Characteristics 1
DC Characteristics (V
DD
= 5.0V ± 10%)
Item
I
nput
Applicable
Pins
SYNC
Other than CKO and RPD
Symbol
V
IH
V
IL
I
OH
I
OL
I
OH
I
OL
I
OH
I
OL
I
I
I
IL
I
IH
I
O2
Measurement
Conditions
Min.
0.7*V
DD
V
SS
Typ.
Max.
5.5
0.3*V
DD
–2.0
–2
Unit
V
voltage
Output
current
RPD
CKO
Input leak
current
Normal input pins
Pull-up resistor connected
Pull-down resistor connected
Output leak
RPD (at high imedance state)
current
V
OH
= V
DD
–0.8V
V
OL
= 0.4V
V
OH
= V
DD
–0.8V
V
OL
= 0.4V
V
OH
= V
DD
/2
V
OL
= V
DD
/2
V
IN
= V
SS
or V
DD
V
IN
= V
SS
V
IN
= V
DD
V
IN
= V
SS
or V
DD
4
2
–18
3.0
–2
–240
10
–40
mA
–3.0
18
2
–10
240
40
µA
Output
voltage
Output
current
12V system output pins
12V system output pins
V
OH
V
OL
I
OH
I
OUT
= –20µA
I
OUT
= 20µA
V
OH
= 11.5V (V
EE
=
12V)
11.9
—
12.0
0.0
—
0.1
–1.0
V
mA
Item
Current
consumption
5V system
12V system
Symbol
I
DD
I
EE
Measurement
Conditions
Note 1)
Note 1)
Min.
Typ.
Max.
25.0
2.0
Unit
mA
Note:
1. Master clock frequency F
CKI
= 12MHz, input conditions V
IH
= V
DD
, V
IL
= V
SS
, no output load.
–4–
CXD2403AR
AC Characteristics
(V
DD
= 5.0V ± 10%)
5V System
Applicable
Item
Pins
Clock input cycle
High level pulse width
Low level pulse width
Clock rise time
Clock fall time
Output rise time
Output fall time
Output rise delay time
Output fall delay time
Symbol
tck
tw (H)
tw (L)
tr (ck)
tf (ck)
tr
tf
tpr
tpf
Measurement
Conditions
Min. Typ. Max. Unit
83
30
30
10
10
20
20
70
70
ns
CKI
Note 4)
SH1, SH2
SH3
5V system
output pins
CL = 10pF
CL = 10pF
CL = 20pF
CL = 20pF
12V System
Output rise time
Output fall time
Cross point time difference
Note 2)
Output rise delay time
Output fall delay time
HCK1, SH1 delay time difference
HCK2, SH2 delay time difference
HCK delay time difference
12V system all
Output pins
Note 3)
VCK1, 2
HCK1, 2
12V system all
ouput pins
Note 3)
HCK1
SH1
HCK2
SH1
HCK1
HCK2
tr
tf
∆t
∆t
tpLH
tpHL
dt1
dt2
tH–tL
CL = 10pF
CL = 40pF
CL = 10pF
CL = 40pF
CL = 10pF
CL = 40pF
CL = 10pF
CL = 40pF
CL = 10pF
CL = 40pF
CL = 40pF
(HCK1, HCK2)
CL = 20pF
(SH1) Note 5)
CL = 40pF
50
80
50
80
15
15
160
180
160
180
125
130
40
ns
80
90
–30
Notes:
2. Applicable to the relationships between HCK1 and HCK2, and VCK1 and VCK2.
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