EQUG33C1H1H-31.796759M TR datasheet, PDF

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EQUG33C1H1H-31.796759M TR: DescriptionLVPECL, Temperature Compensated Voltage Controlled Quartz Crystal Clock Oscillators TCVCXO LVPECL (PECL) 3.3Vdc 6 Pad 2.5mm x 3.2mm Ceramic Surface Mount (SMD) 31.796759MHz ±1.5ppm over 0°C to +50°C; Categoryoscillator; File Size961KB，7 Pages; ManufacturerECLIPTEK; Websitehttp://www.ecliptek.com; Environmental Compliance

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EQUG33C1H1H-31.796759M TR Overview

LVPECL, Temperature Compensated Voltage Controlled Quartz Crystal Clock Oscillators TCVCXO LVPECL (PECL) 3.3Vdc 6 Pad 2.5mm x 3.2mm Ceramic Surface Mount (SMD) 31.796759MHz ±1.5ppm over 0°C to +50°C

EQUG33C1H1H-31.796759M TR Parametric

Parameter Name	Attribute value
Brand Name	Ecliptek
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	SMD 2.5mm x 3.2mm
Contacts	6
Manufacturer packaging code	SMD 2.5mm x 3.2mm
Reach Compliance Code	163
Is Samacsys	N
Base Number Matches	1

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EQUG33C1H1H-31.796759M

REGULATORY COMPLIANCE

2011/65 +

2015/863

(Data Sheet downloaded on Sep 5, 2020)

191 SVHC

ITEM DESCRIPTION

Temperature Compensated Voltage Controlled Quartz Crystal Clock Oscillators TCVCXO LVPECL (PECL) 3.3Vdc 6 Pad 2.5mm

x 3.2mm Ceramic Surface Mount (SMD) 31.796759MHz 0°C to +50°C

ELECTRICAL SPECIFICATIONS

Nominal Frequency

Frequency Stability

Frequency Stability vs. Frequency

Tolerance

Frequency Stability vs. Input Voltage

Frequency Stability vs. Load

Frequency Stability vs. Reflow

Frequency Stability vs. Aging

Operating Temperature Range

Supply Voltage

Input Current

Output Voltage Logic High (Voh)

Output Voltage Logic Low (Vol)

Rise/Fall Time

Duty Cycle

Load Drive Capability

Output Logic Type

Control Voltage

Frequency Deviation

Linearity

Transfer Function

Modulation Bandwidth

Input Impedance

Phase Noise

31.796759MHz

±1.5ppm Maximum (Inclusive of Operating Temperature Range, at Vdd=3.3Vdc, at Vc=1.5Vdc)

±2.0ppm Maximum (at 25°C ±2°C, at Vdd=3.3Vdc, at Vc=1.5Vdc ±0.1Vdc, Pre-Reflow)

±0.2ppm Maximum (±5%)

±0.2ppm Maximum (±2pF)

±1.0ppm Maximum (at 25°C, 24 hours after reflow, 1 time)

±1ppm/Year Maximum (at 25°C)

0°C to +50°C

3.3Vdc ±5%

75mA Maximum

Vdd-1.025Vdc Minimum, 2.4Vdc Typical, Vdd-0.6Vdc Maximum

Vdd-1.85Vdc Minimum, 1.6Vdc Typical, Vdd-1.62Vdc Maximum

300pSec Maximum (Measured at 10% to 90% of Waveform)

50 ±5(%) (Measured at 50% of Waveform)

50 Ohms into Vdd-2Vdc

LVPECL

1.5Vdc ±1.0Vdc

±8ppm Minimum

10% Maximum

Positive Transfer Characteristic

10kHz Minimum (Measured at -3dB)

1MOhms Minimum

-64dBc/Hz at 10Hz offset; -96dBc/Hz at 100Hz offset; -124dBc/Hz at 1kHz offset; -131dBc/Hz at 10kHz offset; -

132dBc/Hz at 100kHz offset; -149dBc/Hz at 1MHz offset; -157dBc/Hz at 10MHz offset; -159dBc/Hz at 20MHz offset (All

Values are Typical)

Output Enable (OE)

90% of Vdd Minimum or No Connect to Enable Output and Complementary Output

10% of Vdd Maximum to Disable Output and Complementary Output (High Impedance)

100nSec Maximum

50nSec Maximum

18mA Maximum (Without Load (Pin 2 = Ground))

1.5pSec Maximum (Fj=12kHz to 20MHz (Random))

0.2pSec Typical

2pSec Typical

3pSec Maximum

30pSec Maximum

Output Control Function

Output Control Input Voltage Logic

High (Vih)

Output Control Input Voltage Logic

Low (Vil)

Output Enable Time

Output Disable Time

Output Enable Current

RMS Phase Jitter

Period Jitter (Deterministic)

Period Jitter (Random)

Period Jitter (RMS)

Period Jitter (pk-pk)

www.ecliptek.com | Specification Subject to Change Without Notice | Revision A 09/09/2015 | Page 1 of 7

Ecliptek, LLC

5458 Louie Lane, Reno, NV 89511

1-800-ECLIPTEK or 714.433.1200

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