Peripherals (CIPs) and Intelligent Analog. They are especially suited for battery-powered LCD applications due to an
integrated charge pump, high current I/O drive for backlighting, and battery backup of the Real-Time Clock/Calendar
(RTCC). Active clock tuning of the HFINTOSC provides a highly accurate clock source over voltage and temperature.
The family also features a new 12-bit ADC controller which can automate Capacitive Voltage Divider (CVD) techniques
for advanced touch sensing, averaging, filtering, oversampling and automatic threshold comparison. Other new features
include low-power IDLE and DOZE modes, Device Information Area (DIA), and Memory Access Partition (MAP). These
low-power products are available in 64 pins to support the customer in various LCD and general purpose applications.
Core Features
• C Compiler Optimized RISC Architecture
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Timers:
- Two 8-bit (TMR2/4) Timer with Hardware
Limit Timer Extension (HLT)
- 16-bit (TMR0/1)
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRTE)
• Brown-out Reset (BOR) with Fast Recovery
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
- Variable prescaler selection
- Variable window size selection
- All sources configurable in hardware or
software
• Programmable Code Protection
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF19195/6/7)
- 2.3V to 5.5V (PIC16F19195/6/7)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
Power-Saving Functionality
• DOZE mode: Ability to run CPU core slower than
the system clock
• IDLE mode: Ability to halt CPU core while internal
peripherals continue operating
• Sleep mode: Lowest power consumption
• Peripheral Module Disable (PMD): Ability to
disable hardware module to minimize power
consumption of unused peripherals
eXtreme Low-Power (XLP) Features
•
•
•
•
Sleep mode: 50 nA @ 1.8V, typical
Watchdog Timer: 500 nA @ 1.8V, typical
Secondary Oscillator: 500 nA @ 32 kHz
Operating Current:
- 8 µA @ 32 kHz, 1.8V, typical
- 32 µA/MHz @ 1.8V, typical
Memory
Up to 56KB Flash Program Memory
Up to 4KB Data SRAM Memory
256 bytes DataEE
Direct, Indirect and Relative Addressing modes
Memory Access Partition (MAP):
- Bootloader write-protect
- Custom partition
• Device Information Area (DIA):
- Temp sensor factory calibrated data
- Fixed Voltage Reference
- Device ID
•
•
•
•
•
Digital Peripherals
• LCD Controller:
- Up to 360 segments
- Charge pump for low-voltage operation
- Contrast control
• Four Configurable Logic Cell Modules (CLC):
- Integrated combinational and sequential logic
2017 Microchip Technology Inc.
Preliminary
DS40001873B-page 1
PIC16(L)F19195/6/7
• Complementary Waveform Generator (CWG):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
• Two Capture/Compare/PWM (CCP) module
• Two 10-Bit PWMs
• Peripheral Pin Select (PPS):
- Enables pin mapping of digital I/O
• Communication:
- Two EUSART, RS-232, RS-485, LIN
compatible
- One SPI/I
2
C, SMBus, PMBus™ compatible
• Up to 59 I/O Pins:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-on-change with edge-select
- Input level selection control (ST or TTL)
- Digital open-drain enable
Flexible Oscillator Structure
• High-Precision Internal Oscillator:
- Active Clock Tuning of HFINTOSC over
voltage and temperature (ACT)
- Selectable frequency range up to 32 MHz
±1% typical
• x2/x4 PLL with Internal and External Sources
• Low-Power Internal 31 kHz Oscillator
(LFINTOSC)
• External 32 kHz Crystal Oscillator (SOSC)
- Oscillator Start-up Timer (OST)
- Ensures stability of crystal oscillator source
• External Oscillator Block with:
- Three external clock modes up to 32 MHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripherals clock
stops
Analog Peripherals
• Analog-to-Digital Converter with Computation
(ADC
2
):
- 12-bit with up to 45 external channels
- Automates math functions on input signals:
averaging, filter calculations, oversampling
and threshold comparison
- Conversion available during Sleep
• Two Comparators:
- (1) Low-Power Clocked Comparator
- (1) High-Speed Comparator
- Fixed Voltage Reference at (non)inverting
input(s)
- Comparator outputs externally accessible
• 5-Bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
• Voltage Reference:
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels
• Zero-Cross Detect Module:
- AC high-voltage zero-crossing detection for
simplifying TRIAC control
- Synchronized switching control and timing
2017 Microchip Technology Inc.
Preliminary
DS40001873B-page 2
2017 Microchip Technology Inc.
TABLE 1:
PIC16(L)F191XX FAMILY TYPES
8-bit/ (with HLT) Timer
LCD Segments (Max)
96
96
184
184
248
248
360
360
360
Temperature Sensor
LCD Charge Pump/
Bias Generator
Y/Y
Y/Y
Y/Y
Y/Y
Y/Y
Y/Y
Y/Y
Y/Y
Y/Y
Device Information
Area
Window Watchdog
Timer (WWDT)
Zero-Cross Detect
Peripheral Module
Disable
Y
Y
Y
Y
Y
Y
Y
Y
Y
Data Sheet Index
Program Flash
Memory (kW/KB)
EUSART/ I
2
C/SPI
CCP/10-bit PWM
Memory Access
Partition
Peripheral Pin
Select
Comparator
16-bit Timer
Data SRAM
(bytes)
12-bit ADC
(ch)
5-bit DAC
Device
PIC16(L)F19155
PIC16(L)F19156
PIC16(L)F19175
PIC16(L)F19176
PIC16(L)F19185
PIC16(L)F19186
PIC16(L)F19195
PIC16(L)F19196
(A)
(A)
(A)
(A)
(A)
(A)
(B)
(B)
(B)
8/14
16/28
8/14
16/28
8/14
16/28
8/14
16/28
32/56
256
256
256
256
256
256
256
256
256
1024
2048
1024
2048
1024
2048
1024
2048
4096
24
24
31
31
39
39
59
59
59
20
20
35
35
43
43
45
45
45
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Y
Y
Y
Y
Y
Y
Y
Y
Y
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
4
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
Y
Y
Y
Y
Y
Y
Y
Y
Y
PIC16(L)F19197
Note
1:
I – Debugging integrated on chip.
Data Sheet Index (Unshaded devices are described in this document):
A.
B.
Future Release
DS40001873
PIC16(L)F191XX Data Sheet, 28/40/44/48-Pin
PIC16(L)F19195/6/7 Data Sheet, Full-Featured 64-Pin Microcontrollers
Debug
(1)
I
I
I
I
I
I
I
I
I
I/O Pins
DataEE
(bytes)
CWG
CLC
Preliminary
DS40001873B-page 3
PIC16(L)F19195/6/7
Note:
For other small form-factor package availability and marking information, please visit
www.microchip.com/packaging
or contact your local sales office.
PIC16(L)F19195/6/7
TABLE 2:
PACKAGES
Device
PIC16(L)F19195
PIC16(L)F19196
PIC16(L)F19197
64-Pin TQFP (10x10)
X
X
X
64-Pin QFN (9x9)
X
X
X
Note:
Pin details are subject to change.
FIGURE 1:
64-PIN TQFP (10X10X1)/QFN (9X9X0.9) PIN DIAGRAM FOR PIC16(L)F19195/6/7
VLCD3
RD0
RH2
RH3
RD1
RD2
RD3
RD4
RD5
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VLCD2
VLCD1
RG0
RG1
RG2
RG3
V
PP
/MCLR/RG5
RG4
V
SS
V
DD
RF7
RF6
RF5
RF4
RF3
RF2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RB0
RB1
RB2
RB3
RB4
RB5
RB6/ICSPCLK
V
SS
RA6
RA7
V
DD
RB7/ICSPDAT
RC5
RC4
RC3
RC2
PIC16(L)F19195/96/97
RF1
RF0
V
BAT
/RA5
RG6
RA3
RA2
RA4
RC1
RC0
RC6
RG7
RH1
Note 1:
QFN package orientation is the same. No leads are present on the QFN package.
2:
See
Table 3
for location of all peripheral functions.
2017 Microchip Technology Inc.
Preliminary
RH0
RC7
RA1
RA0
RD6
RD7
RE3
RE4
RE5
RE6
RE7
DS40001873B-page 4
PIN ALLOCATION TABLES
TABLE 3:
64-Pin TQFP/QFN
Interrupt-on-Change
Zero-Cross Detect
2017 Microchip Technology Inc.
64-PIN ALLOCATION TABLE (PIC16(L)F19195/6/7)
High Current
Timers/SMT
Comparator
Reference
EUSART
Pull-up
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
MSSP
RTCC
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RC0
Note
24
23
22
21
28
27
40
39
48
47
46
45
44
43
42
37
30
1:
2:
3:
4:
5:
6:
ANA0
ANA1
ANA2
ANA3
ANA4
―
ANA6
ANA7
ANB0
ANB1
ANB2
ANB3
ANB4
ANB5
ANB6
ANB7
―
―
―
―
V
REF+
―
―
―
―
―
―
―
―
―
―
―
―
―
C1IN4-
C2IN4-
―
C1IN1+
C2IN1+
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
ZCD
―
―
―
―
―
―
―
―
―
―
―
DAC1
REF+
―
―
―
―
―
―
―
―
―
―
―
DAC1OUT2
―
―
T2IN
(1)
―
―
T0CKI
(1)
―
―
―
―
―
―
―
―
T1G
(1)
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
SCL,
SDA
(1,3,4,5,6)
SCL,
SDA
(1,3,4,5,6)
―
―
―
―
―
―
―
―
―
―
―
―
―
CLCIN0
(1)
CLCIN1
(1)
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
SEG33
SEG18
SEG34
SEG35
SEG14
―
SEG36
SEG37
SEG30
SEG8
SEG9
SEG10
SEG11
SEG29
SEG38
SEG39
―
―
―
―
―
―
―
―
―
INT
(1)
IOCB1
IOCB2
IOCB3
IOCB4
IOCB5
IOCB6
IOCB7
IOCC0
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
V
BAT
CLKOUT
CLKIN
―
Basic
―
―
―
―
―
PWM
CWG
I/O
(2)
ADC
DAC
CCP
CLC
LCD
Preliminary
DS40001873B-page 5
PIC16(L)F19195/6/7
―
―
―
―
―
ICDCLK/
ICSPCLK
ICDDAT/
ICSPDAT
SOSCO
―
―
―
―
―
―
―
―
―
―
―
CLCIN2
(1)
CLCIN3
(1)
―
―
―
T1CKI
(1)
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one or more PORTx pin options.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I
2
C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I
2
C specific or
SMBUS input buffer thresholds.
These are alternative I
2
C logic levels pins.
In I
2
C logic levels configuration, these pins can operate as either SCL or SDA pins.
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