32UC3C2512C-Z2UT datasheet, PDF

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32UC3C2512C-Z2UT: DescriptionRISC Microcontroller, CMOS, MO-026, QFN-64; CategoryMicrocontrollers and processors; File Size19MB，1282 Pages; ManufacturerAtmel (Microchip)

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32UC3C2512C-Z2UT Overview

RISC Microcontroller, CMOS, MO-026, QFN-64

32UC3C2512C-Z2UT Parametric

Parameter Name	Attribute value
Maker	Atmel (Microchip)
Parts packaging code	QFP
package instruction	,
Contacts	64
Reach Compliance Code	unknown
Is Samacsys	N
JESD-30 code	S-XQCC-N64
Number of terminals	64
Package body material	UNSPECIFIED
Package shape	SQUARE
Package form	CHIP CARRIER
Certification status	Not Qualified
surface mount	YES
technology	CMOS
Terminal form	NO LEAD
Terminal location	QUAD
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC
Base Number Matches	1

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Features

•

High Performance, Low Power 32-bit AVR

Microcontroller

Compact Single-cycle RISC Instruction Set Including DSP Instruction Set

Built-in Floating-Point Processing Unit (FPU)

Read-Modify-Write Instructions and Atomic Bit Manipulation

Performing 1.49 DMIPS / MHz

• Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State)

• Up to 49 DMIPS Running at 33 MHz from Flash (0 Wait-State)

– Memory Protection Unit

Multi-hierarchy Bus System

– High-Performance Data Transfers on Separate Buses for Increased Performance

– 16 Peripheral DMA Channels Improves Speed for Peripheral Communication

Internal High-Speed Flash

– 512 Kbytes, 256 Kbytes, 128 Kbytes, 64 Kbytes Versions

– Single Cycle Access up to 33 MHz

– FlashVault

™

Technology Allows Pre-programmed Secure Library Support for End

User Applications

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 4ms Page Programming Time and 8ms Full-Chip Erase Time

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User Defined Configuration Area

Internal High-Speed SRAM, Single-Cycle Access at Full Speed

– 64 Kbytes (512 KB and 256 KB Flash), 32 Kbytes (128 KB Flash), 16 Kbytes (64 KB

Flash)

– 4 Kbytes on the Multi-Layer Bus System (HSB RAM)

External Memory Interface on AT32UC3C0 Derivatives

– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)

Interrupt Controller

– Autovectored Low Latency Interrupt Service with Programmable Priority

System Functions

– Power and Clock Manager

– Internal 115KHz (RCSYS) and 8MHz/1MHz (RC8M) RC Oscillators

– One 32 KHz and Two Multipurpose Oscillators

– Clock Failure detection

– Two Phase-Lock-Loop (PLL) allowing Independent CPU Frequency from USB or

CAN Frequency

Windowed Watchdog Timer (WDT)

Asynchronous Timer (AST) with Real-Time Clock Capability

– Counter or Calendar Mode Supported

Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency

Ethernet MAC 10/100 Mbps interface

– 802.3 Ethernet Media Access Controller

– Supports Media Independent Interface (MII) and Reduced MII (RMII)

Universal Serial Bus (USB)

– Device 2.0 and Embedded Host Low Speed and Full Speed

– Flexible End-Point Configuration and Management with Dedicated DMA Channels

– On-chip Transceivers Including Pull-Ups

One 2-channel Controller Area Network (CAN)

– CAN2A and CAN2B protocol compliant, with high-level mailbox system

–

•

32-bit AVR

Microcontroller

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AT32UC3C064C

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AT32UC3C1256C

AT32UC3C1128C

AT32UC3C164C

AT32UC3C2512C

AT32UC3C2256C

AT32UC3C2128C

AT32UC3C264C

•

32117A–10/2010

AT32UC3C

1. Description

The AT32UC3C is a complete System-On-Chip microcontroller based on the AVR32UC RISC

processor running at frequencies up to 66 MHz. AVR32UC is a high-performance 32-bit RISC

microprocessor core, designed for cost-sensitive embedded applications, with particular empha-

sis on low power consumption, high code density and high performance.

The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-

troller for supporting modern operating systems and real-time operating systems. Using the

Secure Access Unit (SAU) together with the MPU provides the required security and integrity.

Higher computation capabilities are achievable either using a rich set of DSP instructions or

using the floating-point instructions.

The AT32UC3C incorporates on-chip Flash and SRAM memories for secure and fast access.

For applications requiring additional memory, an external memory interface is provided on

AT32UC3C0 derivatives.

The Memory Direct Memory Access controller (MDMA) enables transfers of block of data from

memories to memories without processor involvement.

The Peripheral Direct Memory Access (PDCA) controller enables data transfers between periph-

erals and memories without processor involvement. The PDCA drastically reduces processing

overhead when transferring continuous and large data streams.

The AT32UC3C incorporates on-chip Flash and SRAM memories for secure and fast access.

The FlashVault technology allows secure libraries to be programmed into the device. The secure

libraries can be executed while the CPU is in Secure State, but not read by non-secure software

in the device. The device can thus be shipped to end custumers, who are able to program their

own code into the device, accessing the secure libraries, without any risk of compromising the

proprietary secure code.

The Power Manager improves design flexibility and security. Power monitoring is supported by

on-chip Power-On Reset (POR), Brown-Out Detectors (BOD18, BOD33, BOD50). The CPU

runs from the on-chip RC oscillators, the PLLs, or the Multipurpose Oscillators. The Asynchro-

nous Timer (AST) combined with the 32 KHz oscillator keeps track of the time. The AST can

operate in counter or calendar mode.

The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde-

pendently programmed to perform frequency measurement, event counting, interval

measurement, pulse generation, delay timing, and pulse width modulation.

The PWM module provides four channels with many configuration options including polarity,

edge alignment and waveform non overlap control. The PWM channels can operate indepen-

dently, with duty cycles set independently from each other, or in interlinked mode, with multiple

channels updated at the same time. It also includes safety feature with fault inputs and the ability

to lock the PWM configuration registers and the PWM pin assignment.

The AT32UC3C also features many communication interfaces for communication intensive

applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like

flexible CAN, USB and Ethernet MAC are available. The USART supports different communica-

tion modes, like SPI mode and LIN mode.

The Inter-IC Sound Controller (I2SC) provides a 5-bit wide, bidirectional, synchronous, digital

audio link with off-chip audio devices. The controller is compliant with the I2S bus specification.

32117A–10/2010

AT32UC3C

The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time

thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device

like a USB Flash disk or a USB printer to be directly connected to the processor.

The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC module

provides on-chip solutions for network-connected devices.

The Peripheral Event Controller (PEVC) allows to redirect events from one peripheral or from

input pins to another peripheral. It can then trigger, in a deterministic time, an action inside a

peripheral without the need of CPU. For instance a PWM waveform can directly trigger an ADC

capture, hence avoiding delays due to software interrupt processing.

The AT32UC3C features analog functions like ADC, DAC, Analog comparators. The ADC inter-

face is built around a 12-bit pipelined ADC core and is able to control two independent 8-channel

or one 16-channel. The ADC block is able to measure two different voltages sampled at the

same time. The analog comparators can be paired to detect when the sensing voltage is within

or outside the defined reference window.

Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels

functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers

robust sensing and included fully debounced reporting of touch keys and includes Adjacent Key

Suppression

(AKS

) technology for unambiguous detection of key events. The easy-to-use

QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications.

AT32UC3C integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive

real-time trace, full-speed read/write memory access in addition to basic runtime control. The

Nanotrace interface enables trace feature for aWire- or JTAG-based debuggers. The single-pin

aWire interface allows all features available through the JTAG interface to be accessed through

the RESET pin, allowing the JTAG pins to be used for GPIO or peripherals.

32117A–10/2010

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