531CC143M000DGR datasheet, PDF

Datasheet> All Categories > oscillator> 531CC143M000DGR

531CC143M000DGR: DescriptionCMOS Output Clock Oscillator, 143MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; Categoryoscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531CC143M000DGR Overview

CMOS Output Clock Oscillator, 143MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531CC143M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Is Samacsys	N
Other features	TAPE AND REEL
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	143 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS
physical size	7.0mm x 5.0mm x 1.85mm
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Simple timing control circuit

Baiyun brand BCD-180A refrigerator circuit

Four-channel infrared remote control remote transmitter circuit

AND logic circuit

Precise second pulse signal generator

Main circuit of medium frequency power supply with fast short circuit protection

ADC12 usage in MSP430F5XXX: , The AD part of the usage processmainly configures the clock, reference source, sampling channel, sampling mode, storage and sample hold of the ADC12 module.Let's go through it one by one. The first ...; 火辣西米秀 Microcontroller MCU

Please help me analyze the sentence: unsigned char addr1,addr2; unsigned int i,addr=address; addr1 = addr>>8; //Redundant? addr1 = addr1<<6; //Redundant? addr1|= CMD_RMM; addr2 = (unsigned char)addr; Where address=0x04;CMD_RMM=0x0e; Why ...; luoddy520 Microcontroller MCU

When developing a bootloader under wince6.0, I cannot use new or delete. What should I do?: When developing a bootloader under wince6.0, I cannot use new and delete. It prompts that localalloc and localfree cannot be implemented. Is there any way to solve this problem?...; brybert Embedded System

EADS releases 350MHz digital trunking system: [i=s]This post was last edited by jameswangsynnex on 2015-3-3 19:59[/i] Recently, at the China International Police Equipment Expo, EADS released the TETRA system with a dedicated 350MHz frequency ban...; aifang Mobile and portable

How to use code to display the program in the tray?: I am now using a program under WinCE to call the MengTian input method, but after calling it up, an arrow will be displayed in the lower right corner, and the input operation interface is not directly...; jielii Embedded System

FPGA (cyclone4) development board free education program: The second phase of the FPGA (cyclone4) development board free aid program - the board upgrade has begun, everyone is welcome to participate!significance:Use the development board from the blog of sen...; EEWORLD社区 FPGA/CPLD

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components