DS1WM
Synthesizable 1-Wire Bus Master
www.maxim-ic.com
FEATURES
Memory maps into any standard byte-wide data
bus.
Eliminates CPU “bit-banging” by internally
generating all 1-Wire timing and control signals.
Generates interrupts to provide for more efficient
programming.
Search ROM Accelerator relieves CPU from any
single bit operations on the 1-Wire
®
Bus.
Capable of running off any system clock from 4
MHz to 128 MHz.
Small size: all digital design, only 3470 gates.
Applications include any circuit containing a 1-
Wire communication bus.
Supports standard and overdrive 1-Wire
communication speeds
Supports strong pull-up specifications.
Master available in both Verilog and VHDL
Supports single bit transmissions.
Provides added support for long line conditions.
Customer ASIC
Internal
Data Bus
1-Wire
Master
TM
1-Wire
Bus
Strong
Pull-up
control
Interrupt
DESCRIPTION
As more 1-Wire devices become available, more and more users have to deal with the demands of
generating 1-Wire signals to communicate to them. This usually requires “bit-banging” a port pin on a
microprocessor, and having the microprocessor perform the timing functions required for the 1-Wire
protocol. While 1-Wire transmission can be interrupted mid-byte, it cannot be interrupted during the
“low” time of a bit time slot; this means that a CPU will be idled for up to 60 microseconds for each bit
sent and at least 480 microseconds when generating a 1-Wire reset. The 1-Wire Master helps users handle
communication to 1-Wire devices in their system without tying up valuable CPU cycles. Integrated into a
user’s ASIC as a 1-Wire port, the Verilog or VHDL core uses little chip area (3470 gates plus 2 bond
pads).
This circuit is designed to be memory mapped into the user’s system and provides complete control of the
1-Wire bus through 8-bit or single commands. The host CPU loads commands, reads and writes data, and
sets interrupt control through six individual registers. All of the timing and control of the 1-Wire bus are
generated within. The host merely needs to load a command or data and then may go on about its
business. When bus activity has generated a response that the CPU needs to receive, the 1-Wire Master
sets a status bit and, if enabled, generates an interrupt to the CPU. In addition to write and read
simplification, the 1-Wire Master also provides a Search ROM Accelerator function relieving the CPU
from having to perform the complex single-bit operations on the 1-Wire bus.
1-Wire is a registered trademark of Dallas Semiconductor Corp., a wholly owned subsidiary of Maxim Integrated Products, Inc.
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The operation of the 1-Wire bus is described in detail in the
Book of iButton Standards
[1]; therefore,
the details of that will not be discussed in this document. Each slave device, in general, has its own set of
commands that are described in detail in that device’s data sheet. The user is referred to those documents
for detail on specific slave implementations.
®
BLOCK DIAGRAM
INTR
INTERRUPT REGISTER
INT ENABLE REGISTER
INTERRUPT
CONTROL
LOGIC
D0-D7
DATA BUS
BUFFER
CONTROL REGISTER
COMMAND REGISTER
A0
A1
A2
ADS
RD
WR
EN
RECEIVE BUFFER
Rx SHIFT REGISTER
CONTROL
LOGIC
TRANSMIT BUFFER
1-WIRE
TIMING
AND
CONTROL
DQ
OWSTPZ
Tx SHIFT REGISTER
MR
MASTER
RESET
CLOCK DIV REGISTER
CLK
CLOCK
DIVIDER
PIN DESCRIPTIONS
The following describes the function of all the block I/O pins. In the following descriptions, 0 represents
logic low and 1 represents logic high.
A0, A1, A2,
Register Select: Address signals connected to these three inputs select a register for the CPU
to read from or write to during data transfer. A table of registers and their addresses is shown below.
iButton is a registered trademark of Dallas Semiconductor Corp., a wholly owned subsidiary of Maxim Integrated Products, Inc.
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Register Addresses
A2
0
0
0
0
1
1
A1
0
0
1
1
0
0
A0
0
1
0
1
0
1
Register
Command Register (read/write)
Transmit Buffer (write), Receive Buffer (read)
Interrupt Register (read)
Interrupt Enable Register (read/write)
Clock Divisor Register (read/write)
Control Register (read/write)
ADS
, Address Strobe: The positive edge of an active Address Strobe (
ADS
) signal latches the Register
Select (A0, A1, A2) into an internal latch. Provided that setup and hold timings are observed,
ADS
may
be tied low making the latch transparent.
CLK,
Clock Input: This is a (preferably) 50% duty cycle clock that can range from 4 MHz to 128 MHz.
This clock provides the timing for the 1-Wire bus.
D7-D0,
Data Bus: This bus comprises eight input/output lines. The bus provides bi-directional
communications between the 1-Wire master and the CPU. Data, control words, and status information are
transferred via this D7-D0 Data Bus.
DQ,
1-Wire Data Line: This open-drain line is the 1-Wire bi-directional data bus. 1-Wire slave devices
are connected to this pin. This pin must be pulled high by an external resistor, nominally 5 kΩ.
EN
, Enable: When
EN
is low, the 1-Wire master is enabled; this signal acts as the device chip enable.
This enables communication between the 1-Wire master and the CPU.
INTR,
Interrupt: This line goes to its active state whenever any one of the interrupt types has an active
high condition and is enabled via the Interrupt Enable Register. The INTR signal is reset to an inactive
state when the Interrupt Register is read.
MR,
Master Reset: When this input is high, it clears all the registers and the control logic of the 1-Wire
master, and sets INTR to its default inactive state, which is HIGH.
RD
, Read: This pin drives the bus during a read cycle. When the circuit is enabled, the CPU can read
status information or data from the selected register by driving
RD
low.
RD
and
WR
should never be
low simultaneously; if they are,
WR
takes precedence.
STPZ,
Strong Pull-up Enable: This pin drives the gate of the p-channel transistor which bypasses the
weak pull-up resistor in order to provide the slave device with a stiff power supply for high current
applications.
WR
, Write: This pin drives the bus during a write cycle. When
WR
is low while the circuit is enabled,
the CPU can write control words or data into the selected register.
RD
and
WR
should never be low
simultaneously; if they are,
WR
takes precedence.
OPERATION – COMMANDS
The 1-Wire Master can generate two special commands on the bus in addition to reading and writing. The
first is a 1-Wire reset, which must precede any command given on the bus. Secondly, the 1-Wire Master
can be placed into Search ROM Accelerator mode to prevent the host from having to perform single bit
manipulations of the bus during a Search ROM operation (0xF0h). For details on the reset or Search
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ROM command see [1]. In addition to these two functions, the Command Register contains two bits to
bypass the 1-Wire Master features and control the 1-Wire bus directly.
Command Register (Read/Write)
Addr. 00h
X
MSB
Default: 08h
OW_IN
FOW
SRA
1WR
LSB
X
X
X
Bit 3 - OW_IN:
OW Input. This bit always reflects the current state of the 1-Wire line.
Bit 2 - FOW:
Force One Wire. This bit can be used to bypass 1-Wire Master operations and drive the bus
directly if needed. Setting this bit high will drive the bus low until it is cleared or the 1-Wire Master reset.
While the 1-Wire bus is held low no other 1-Wire Master operations will function. By controlling the
length of time this bit is set and the point when the line is sampled, any 1-Wire communication can be
generated by the host controller. To prevent accidental writes to the bus, the EN_FOW bit in the
CONTROL register must be set to a 1 before the FOW bit will function. This bit is cleared to a 0 on
power-up or master reset.
Bit 1 - SRA:
Search ROM Accelerator. When this bit is set, the 1-Wire Master will switch to Search
ROM Accelerator mode. (See “Search ROM Accelerator Description” for the rest of the function
description.) When this bit is set to 0, the master will function in its normal mode. This bit is cleared to 0
on a power-up or master reset.
Bit 0 - 1WR:
1-Wire Reset. If this bit is set a reset will be generated on the 1-Wire bus. Setting this bit
automatically clears the SRA bit. The 1WR bit will be automatically cleared as soon as the 1-Wire reset
completes. The 1-Wire Master will set the Presence Detect interrupt flag (PD) when the reset is complete
and sufficient time for a presence detect to occur has passed. The result of the presence detect will be
placed in the interrupt register bit PDR. If a presence detect pulse was received PDR will be cleared,
otherwise it will be set.
Search ROM Accelerator Description
The Search ROM Accelerator Mode presupposes that a Reset followed by the Search ROM command
(0xF0h) has already been issued on the 1-Wire bus. For details on how the Search ROM is actually done
in the 1-Wire system, please see [1]. Simply put, the algorithm specifies that the bus master reads two bits
(a bit and its complement), then writes a bit to specify which devices should remain on the bus for further
processing.
After the 1-Wire Master is placed in Search ROM Accelerator mode, the CPU must send 16 bytes to
complete a single Search ROM pass on the 1-Wire bus. These bytes are constructed as follows:
First byte
7
6
5
4
3
2
1
0
r
3
x
3
16
th
byte
7
6
r
2
5
x
2
4
r
1
3
x
1
2
r
0
1
x
0
0
r
63
x
63
r
62
x
62
r
61
x
61
r
60
x
60
In this scheme, the index (values from 0 to 63, “n”) designates the position of the bit in the ROM ID of a
1-Wire device. The character “x” marks bits that act as a filler and do not require a specific value (don’t
care bits). The character “r” specifies the selected bit value to write at that particular bit in case of a
conflict during the execution of the ROM search.
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For each bit position n (values from 0 to 63) the 1-Wire Master will generate three time slots on the 1-
Wire bus. These are referenced as:
b0
b1
b2
for the first time slot (read data)
for the second time slot (read data) and
for the third time slot (write data).
The 1-Wire Master determines the type of time slot b2 (write 1 or write 0) as follows:
b2
= r
n
if conflict (as chosen by the host)
= b
0
if no conflict (there is no alternative)
= 1 if error (there is no response)
The response bytes that will be in the data register for the CPU to read during a complete pass through a
Search ROM function using the Search Accelerator consists of 16 bytes as follows:
first byte
7
6
5
4
3
2
1
0
r’
3
d
3
et cetera
16
th
byte
7
6
r’
2
d
2
r’
1
d
1
r’
0
d
0
5
4
3
2
1
0
r’
63
d
63
r’
62
d
62
r’
61
d
61
r’
60
d
60
As before, the index designates the position of the bit in the ROM ID of a 1-Wire device. The character
“d” marks the discrepancy flag in that particular bit position. The discrepancy flag will be 1 if there is a
conflict or no response in that particular bit position and 0 otherwise. The character “r’” marks the
actually chosen path at that particular bit position. The chosen path is identical to b2 for the particular bit
position of the ROM ID.
To perform a Search ROM sequence one starts with all bits r
n
being 0s. In case of a bus error, all
subsequent response bits r’
n
are 1’s until the Search Accelerator is deactivated by writing 0 to bit 1 of the
Command register. Thus, if r’
63
and d
63
are both 1, an error has occurred during the search procedure and
the last sequence has to be repeated. Otherwise r’
n
(n=0…63) is the ROM code of the device that has
been found and addressed. When the Search ROM process is complete the SRA bit should be cleared in
order to release the 1-Wire Master from Search ROM Accelerator Mode.
For the next Search ROM sequence one re-uses the previous set r
n
(n=0…63) but sets r
m
to 1 with “m”
being the index number of the highest discrepancy flag that is 1 and sets all r
i
to 0 with i > m. This
process is repeated until the highest discrepancy occurs in the same bit position for two consecutive
passes.
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