74LVC1G38GW datasheet, PDF - EEWORLD Datasheet

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74LVC1G38GW: Description2-input NAND gate; open drain; Categorylogic logic; File Size70KB，15 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LVC1G38GW Overview

2-input NAND gate; open drain

74LVC1G38GW Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	TSSOT
package instruction	1.25 MM, PLASTIC, MO-203, SC-88A, SOT353-1, TSSOP-5
Contacts	5
Reach Compliance Code	compli
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G5
JESD-609 code	e3
length	2.05 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of functions	1
Number of entries	2
Number of terminals	5
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	OPEN-DRAIN
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP5/6,.08
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Su	5.7 ns
propagation delay (tpd)	12.5 ns
Certification status	Not Qualified
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	1.25 mm

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74LVC1G38

2-input NAND gate; open drain

Rev. 03 — 27 August 2007

Product data sheet

1. General description

The 74LVC1G38 provides a 2-input NAND function.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this

device as translator in a mixed 3.3 V and 5 V environment.

This device is fully speciﬁed for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing the damaging backﬂow current through the device

when it is powered down.

2. Features

Wide supply voltage range from 1.65 V to 5.5 V

5 V tolerant outputs for interfacing with 5 V logic

High noise immunity

Complies with JEDEC standard:

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8-B/JESD36 (2.7 V to 3.6 V).

ESD protection:

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

±24

mA output drive (V

= 3.0 V)

CMOS low power consumption

Open drain outputs

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

Multiple package options

Speciﬁed from

−40 °C

to +125

°C.

74LVC1G38GW Related Products

	74LVC1G38GW	74LVC1G38	74LVC1G38GV	74LVC1G38GM	74LVC1G38GF
Description	2-input NAND gate; open drain	2-input NAND gate; open drain	2-input NAND gate; open drain	2-input NAND gate; open drain	2-input NAND gate; open drain
Is it Rohs certified?	conform to	-	conform to	conform to	conform to
Maker	NXP	-	NXP	NXP	NXP
Parts packaging code	TSSOT	-	SC-74A	SON	SON
package instruction	1.25 MM, PLASTIC, MO-203, SC-88A, SOT353-1, TSSOP-5	-	PLASTIC, SOT-753, SC-74A, 5 PIN	VSON, SOLCC6,.04,20	VSON, SOLCC6,.04,14
Contacts	5	-	5	6	6
Reach Compliance Code	compli	-	compli	compli	compli
series	LVC/LCX/Z	-	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	R-PDSO-G5	-	R-PDSO-G5	R-PDSO-N6	S-PDSO-N6
JESD-609 code	e3	-	e3	e3	e3
length	2.05 mm	-	2.9 mm	1.45 mm	1 mm
Load capacitance (CL)	50 pF	-	50 pF	50 pF	50 pF
Logic integrated circuit type	NAND GATE	-	NAND GATE	NAND GATE	NAND GATE
MaximumI(ol)	0.024 A	-	0.024 A	0.024 A	0.024 A
Humidity sensitivity level	1	-	1	1	1
Number of functions	1	-	1	1	1
Number of entries	2	-	2	2	2
Number of terminals	5	-	5	6	6
Maximum operating temperature	125 °C	-	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-	-40 °C	-40 °C	-40 °C
Output characteristics	OPEN-DRAIN	-	OPEN-DRAIN	OPEN-DRAIN	OPEN-DRAIN
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	-	TSSOP	VSON	VSON
Encapsulate equivalent code	TSSOP5/6,.08	-	TSOP5/6,.11,37	SOLCC6,.04,20	SOLCC6,.04,14
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	SQUARE
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE
method of packing	TAPE AND REEL	-	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	-	260	260	260
power supply	3.3 V	-	3.3 V	3.3 V	3.3 V
Prop。Delay @ Nom-Su	5.7 ns	-	5.7 ns	5.7 ns	5.7 ns
propagation delay (tpd)	12.5 ns	-	12.5 ns	12.5 ns	12.5 ns
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.1 mm	-	1.1 mm	0.5 mm	0.5 mm
Maximum supply voltage (Vsup)	5.5 V	-	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	1.65 V	-	1.65 V	1.65 V	1.65 V
Nominal supply voltage (Vsup)	3.3 V	-	3.3 V	3.3 V	3.3 V
surface mount	YES	-	YES	YES	YES
technology	CMOS	-	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	-	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	Tin (Sn)	-	Tin (Sn)	Tin (Sn)	Tin (Sn)
Terminal form	GULL WING	-	GULL WING	NO LEAD	NO LEAD
Terminal pitch	0.65 mm	-	0.95 mm	0.5 mm	0.35 mm
Terminal location	DUAL	-	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	-	30	30	30
width	1.25 mm	-	1.5 mm	1 mm	1 mm

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