(Host Clock Signal Level) clock output from a clock
input reference of 25MHz. The input reference may be derived
from an external source or by the addition of a 25MHz crystal to
the on-chip crystal oscillator. An external reference may be applied
to the XTAL_IN pin with the XTAL_OUT pin left floating.
F
EATURES
•
Two 0.7V current mode differential HCSL output pairs
•
Crystal oscillator interface, 25MHz
•
Output frequency: 100MHz
•
RMS period jitter: 3ps (maximum)
•
Output skew: 35ps (maximum)
•
Cycle-to-cyle jitter: 35ps (maximum)
•
I
2
C support with readback capabilities up to 400kHz
•
Spread Spectrum for electromagnetic interference (EMI)
reduction
•
3.3V operating supply mode
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
The device offers spread spectrum clock output for reduced EMI
applications. An I
2
C bus interface is used to enable or disable
spread spectrum operation as well as select either a down spread
value of -0.35% or -0.5%.
The ICS841S02I is available in both standard and lead-free
20-Lead TSSOP packages.
B
LOCK
D
IAGRAM
25MHz
P
IN
A
SSIGNMENT
PLL
Divider
Network
SRCT[1:2]
SRCC[1:2]
V
SS
_
SRC
V
DD
_
SRC
SRCT2
SRCC2
SRCT1
SRCC1
V
SS
_
SRC
V
DD
_
SRC
V
SS
_
SRC
IREF
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
_
SRC
SDATA
SCLK
nc
XTAL_OUT
XTAL_IN
V
DD
_
REF
V
SS
_
REF
V
DDA
V
SSA
XTAL_IN
OSC
XTAL_OUT
SDATA
Pullup
SCLK
Pullup
I
2
C
Logic
IREF
ICS841S02I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
PCI EXPRESS CLOCK GENERATOR
1
ICS841S02BGI REV. C NOVEMBER 1, 2007
ICS841S02I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 7, 9
2, 8, 20
3, 4
5, 6
10
11
12
13
14
Name
V
SS_SRC
V
DD_SRC
SRCT2, SRCC2
SRCT1, SRCC1
IREF
V
SSA
V
DDA
V
SS_REF
V
DD_REF
Type
Power
Power
Output
Output
Input
Power
Power
Power
Power
Description
Ground for core and SRC outputs.
Power supply for core and SRC outputs.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
A fixed precision resistor (475W) from this pin to ground provides a
reference current used for differential current-mode SRCCx, SRCTx
clock outputs.
Analog ground pin.
Power supply for PLL.
Ground for crystal interface
Power supply for crystal interface.
Crystal oscillator interface. XTAL_IN is the input.
15, 16
XTAL_IN, XTAL_OUT
Input
XTAL_OUT is the output.
17
nc
Unused
No connect.
SMBus compatible SCLK. This pin has an internal pullup resistor,
18
SCLK
Input
Pullup but is in high impedance in powerdown mode.
LVCMOS/LVTTL interface levels.
SMBus compatible SDATA. This pin has an internal pullup resistor,
Input/
19
SDATA
Pullup but is in high impedance in powerdown mode.
Output
LVCMOS/LVTTL interface levels.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
C
OUT
L
IN
Parameter
Input Capacitance
Input Pullup Resistor
Output Pin Capacitance
Pin Inductance
3
Test Conditions
Minimum
Typical
4
51
5
7
Maximum
Units
pF
kΩ
pF
nH
IDT
™
/ ICS
™
PCI EXPRESS CLOCK GENERATOR
2
ICS841S02BGI REV. C NOVEMBER 1, 2007
ICS841S02I
PCI EXPRESS™ CLOCK GENERATOR
PRELIMINARY
S
ERIAL
D
ATA
I
NTERFACE
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, can be individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting upon power-up, and therefore, use of this
interface is optional. Clock device register changes are nor-
mally made upon system initialization, if any are required. The
interface cannot be used during system operation for power
management functions.
D
ATA
P
ROTOCOL
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-
set of the indexed byte is encoded in the command code, as
described in
Table 3A.
The block write and block read protocol is outlined in
Table 3B,
while
Table 3C
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
T
ABLE
3A. C
OMMAND
C
ODE
D
EFINITION
BIT
7
6:5
4:0
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation.
Chip select address, set to "00" to access device.
Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be
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