FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer
G
ENERAL
D
ESCRIPTION
The 843204I-01 is a 4 output LVPECL Synthe-sizer optimized
to generate Gigabit Ethernet and SONET reference clock
frequencies and is a member of the HiPerClocks
TM
family
of high perfor mance clock solutions from IDT. Using
a 19.44MHz and 25MHz, 18pF parallel resonant crystal,
155.52MHz and 156.25MHz frequencies can be generated.
The 843204I-01 uses IDT’s FemtoClock
TM
low phase noise VCO
technology and can achieve 1ps or lower typical RMS phase jitter.
843204I-01
DATA SHEET
F
EATURES
• Four 3.3V LVPECL outputs
• Selectable crystal oscillator interface or clock inputs
• Supports the following output frequencies: 155.52MHz
and 156.25MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz - 13MHz): 0.6ps (typical)
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.7ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• For functional replacement part us 8T49N285
B
LOCK
D
IAGRAM
nPLL_BYPASS_A
Pullup
IN_SELA
Pullup
CLK0
Pulldown
25MHz
P
IN
A
SSIGNMENT
nQA1
QA1
nQA0
QA0
nc
V
CCO
_
A
SELA1
SELA0
nPLL_BYPASS_A
nc
nc
nc
nc
XTAL_IN1
XTAL_OUT1
CLK1
nCLK1
IN_SELB
V
CCO
_
B
nc
QB0
nQB0
QB1
nQB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
IN_SELA
CLK0
XTAL_IN0
XTAL_OUT0
nc
V
EE
OEA0
OEA1
V
CC
V
CCA
nPLL_BYPASS_B
nc
SELB0
V
EE
OEB0
OEB1
V
CC
SELB1
V
CCA
nc
nc
nc
nc
nc
SELA0
OEA0
QA0
XTAL_IN0
OSC
XTAL_OUT0
PLL
÷4
156.25MHz
0
1
SELA1
OEA1
QA1
nQA1
nQA0
625MHz
nPLL_BYPASS_B
Pullup
IN_SELB
Pullup
CLK1
Pulldown
0
1
nCLK1
Pullup/pulldown
19.44MHz
SELB0
OEB0
QB0
nQB0
XTAL_IN1
0
OSC
XTAL_OUT1
PLL
622.08MHz
÷4
155.52MHz
1
SELB0
OEB1
843204I-01
QB1
nQB1
0
1
48 Lead TSSOP
6.1mm x 12.5mm x 0.925mm
package body
G Package
Top View
843204I-01 REVISION A 11/5/15
1
©2015 Integrated Device Technology, Inc.
843204I-01 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5, 10, 11, 12,
13, 20, 25, 26,
27, 28, 29, 37,
44
6
7
8
9
14,
15
16
17
18
19
21, 22
23, 24
30, 39
31
32, 40
33
34
35, 43
36
38
41
42
45,
46
47
48
Name
nQA1, QA1
nQA0, QA0
nc
V
CCO_A
SELA1
SELA0
nPLL_BYPASS_A
XTAL_IN1, XTAL_
OUT1
CLK1
nCLK1
IN_SELB
V
CCO_B
QB0, nQB0
QB1, nQB1
V
CCA
SELB1
V
CC
OEB1
OEB0
V
EE
SELB0
nPLL_BYPASS_B
OEA1
OEA0
XTAL_OUT0,
XTAL_IN0
CLK0
IN_SELA
Type
Output
Output
Unused
Power
Input
Input
Input
Input
Input
Input
Input
Power
Ouput
Ouput
Power
Input
Power
Input
Input
Power
Input
Input
Input
Input
Input
Input
Input
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pulldown
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
No connect.
Output supply pin for Bank A outputs.
Select pin. When HIGH, selects QA1/nQA1 at 155.52MHz. When LOW,
selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels.
Select pin. When HIGH, selects QA0/nQA0 at 155.52MHz. When LOW,
Pulldown
selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels.
Pullup
When LOW, PLL is bypassed. When HIGH, PLL output is active.
Parallel resonant crystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Pulldown Non-inverting differential clock input.
Pullup/
Inverting differential clock input. V
DD
/2 bias voltage when left floating.
Pulldown
Select pin. When HIGH, selects XTAL1 inputs. When LOW, selects CLK1,
Pullup
nCLK1 inputs. LVCMOS/LVTTL interface levels.
Output supply pin for Bank B outputs.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Analog supply pins.
Select pin. When HIGH, selects QB1/nQB1 at 155.52MHz. When LOW,
selects QB1/nQB1 at 156.25MHz. LVCMOS/LVTTL interface levels.
Core supply pins.
Output enable pin. QB1/nQB1 outputs are enable.
LVCMOS/LVTTL interface levels.
Output enable pin. QB0/nQB0 outputs are enabled.
LVCMOS/LVTTL interface levels.
Negative supply pins.
Select pin. When HIGH, selects QB0/nQB0 at 155.52MHz. When LOW,
selects QB0/nQB0 at 156.25MHz. LVCMOS/LVTTL interface levels.
When LOW, PLL is bypassed. When HIGH, PLL output is active.
Output enable pin. QA1/nQA1 outpus are enabled.
LVCMOS/LVTTL interface levels.
Output enable pin. QA0/nQA0 outputs are enabled.
LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
Select pin. When HIGH, selects XTAL0 inputs. When LOW, selects CLK0
input. LVCMOS/LVTTL interface levels.
Pulldown LVCMOS/LVTTL clock input.
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
2
Test Conditions
Minimum
Typical
4
51
51
k
k
Ω
Maximum
Units
pF
Ω
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
REVISION A 11/5/15
843204I-01 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
54.8°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V±10%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO_A,
V
CCO_B
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.97
V
CC
– 0.22
2.97
Typical
3.3
3.3
3.3
Maximum
3.63
V
CC
3.63
165
22
Units
V
V
V
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V±10%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
CLK0, SELA0, SELA1
I
IH
Input
High Current
nPLL_BYPASS_A,
nPLL_BYPASS_B, IN_
SELA, IN_SELB, SELB1,
SELB0, OEB0, OEB1,
OEA0, OEA1
CLK0, SELA0, SELA1
I
IL
Input
Low Current
nPLL_BYPASS_A,
nPLL_BYPASS_B, IN_
SELA, IN_SELB, SELB1,
SELB0, OEB0, OEB1,
OEA0, OEA1
V
CC
= V
IN
= 3.63V
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
V
CC
= V
IN
= 3.63V
5
µA
V
CC
= 3.63V, V
IN
= 0V
-5
µA
V
CC
= 3.63V, V
IN
= 0V
-150
µA
REVISION A 11/5/15
3
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
843204I-01 DATA SHEET
T
ABLE
3C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V±10%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLK1,
nCLK1
nCLK1
CLK1
Test Conditions
V
IN
= V
CC
= 3.63V
V
IN
= 0V, V
CC
= 3.63V
V
IN
= 0V, V
CC
= 3.63V
-150
-5
0.15
V
EE
+ 0.5
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
3D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V±10%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Ω
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50 to V
CCO
- 2V.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
XTAL0
XTAL1
Test Conditions
Minimum
Typical
25
19.44
50
7
1
Maximum
Units
MHz
MHz
Ω
pF
mW
Fundamental
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCO_A
= V
CCO_B
= 3.3V±10%, V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
f
OUT
tsk(b)
tjit(Ø)
t
R
/ t
F
odc
Parameter
Output Frequency
Bank Skew; NOTE 1, 2
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
Output Duty Cycle
155.52MHz, (12kHz - 1.3MHz)
156.25MHz, (1.875MHz - 20MHz)
20% to 80%
250
47
0.6
0.7
600
53
Test Conditions
SELB0 = 1; OEB0 = 1
SELA0 = 0; OEA0 = 1
Minimum
Typical
155.52
156.25
60
Maximum
Units
MHz
MHz
ps
ps
ps
ps
%
NOTE 1: Defined as skew within a bank of outputs at the same supply voltags and with equal load conditions.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: See Phase Noise plot.
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
4
REVISION A 11/5/15
843204I-01 DATA SHEET
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
RMS P
HASE
J
ITTER
B
ANK
S
KEW
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
REVISION A 11/5/15
5
FEMTOCLOCKS™ CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
京公网安备 11010802033920号
EEWORLD
