Single Chip GPS LSI
CXD2951GL-4
Description
The CXD2951GL-4 is a dedicated single chip LSI for the GPS (Global Positioning System), satellite-based
location measurement system. This LSI enables the configuration of a single chip system providing a cost-
effective, low-power solution.
Compared with conventional methods, position detection time and sensitivity are substantially improved with
the use of an advanced signal processing scheme. With the integration of both the Radio and baseband blocks
into a single CMOS IC, the CXD2951GL-4 is ideal for use in automotive, cellular handset, handheld navigation,
mobile computing and other location-based applications.
Features
WAAS support
12-channel GPS receiver capable of simultaneously receiving 12 satellites
Reception frequency: 1575.42MHz (L1 band, CA code)
Reference clock (TCXO) frequency: 18.414MHz (GPS, Sony standard),
The unique frequency of major applications is available, such as GSM and W-CDMA. (optional)
13.000MHz (GSM),
14.400MHz (CDMA),
16.368MHz (GPS),
19.800MHz (PDC/CDMA),
26.000MHz (GSM)
32 bits RISC CPU (ARM7TDMI)
288K-bytes Program ROM
72K-bytes Data RAM
Power is supplied only to 8K-byte Data RAM while in backup mode.
System power management
1-channel UART
Internal RTC (Real Time Clock)
10-bit successive approximation system A/D converter
All-in-view positioning
Communication format: Supports NMEA-0183 (Ver 3.01)
1PPS output
<
RADIO
>
Image Rejection Mixer
VCO Tank
IF Filters
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating
the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E05313A5Z
CXD2951GL-4
Package
183 pin VFLGA (Plastic)
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
Supply voltage I/O
Supply voltage core
Supply voltage radio
Input voltage
Output voltage
Operating temperature
Storage temperature
IOV
DD
CV
DD
V
DD
V
I
V
O
Topr
Tstg
–0.5 to +4.6
–0.5 to +2.5
–0.5 to +2.5
–0.5 to +6
–0.5 to +6
–40 to +85
–50 to +150
V
V
V
V
V
°
C
°
C
Recommended Operating Conditions
Supply voltage I/O
IOV
DD
3.0 to 3.6
V
*
Under operation with internal ROM, using no external expansion bus:
IOV
DD
*
Under operation in backup mode:
BKUPIOV
DD
Supply voltage core
Supply voltage radio
Operating temperature
CV
DD
V
DD
Topr
2.5 (Min.)
1.62 to 1.98
1.62 to 1.98
–40 to +85
V
V
V
°
C
2.6 to 3.6
V
Input/Output Pin Capacitance (Baseband)
Input pin capacitance
Output pin capacitance
I/O pin capacitance
C
IN
C
OUT
C
I/O
9 (Max.)
11 (Max.)
11 (Max.)
pF
pF
pF
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CXD2951GL-4
Performance
Baseband
Tracking sensitivity: –152dBm (average) or less
Acquisition sensitivity: –139dBm (average) or less in Normal mode
*
Reference data using the Sony's reference board when using both an antenna of 0dBi and a RF amplifier
with NF
≤
2dB, 25dB gain.
TTFF (Time to First Fix):
Time until initial position measurement after power-on with the following conditions:
Cold Start (without both ephemeris and almanac time): 40s (average) / 50s (95% possibility)
Warm Start (without ephemeris but with almanac time): 33s (average) / 40s (95% possibility)
Hot Start (with both ephemeris and almanac time): 2s (minimum) / 3s (95% possibility)
*
Reference data with elevation angle of 5
°
or more and no interception environment with satellite powers
≥
–130dBm.
Note) “95% possibility” means “position time with 95% possibility”.
Positioning accuracy:
2DRMS: approx. 2m
*
Reference data with elevation angle of 5
°
or more and no interception environment with satellite powers
≥
30dBm.
Measurement data update time: 1s
Power consumption:
50mW (average) while position calculating with tracking satellites in low power mode
120mW (average) while position calculating with acquiring and tracking satellites
*
Reference data using the Sony's reference board when the reference clock input is 18.414MHz, and its
amplitude is 3.3V swing.
1PPS output
1µs or less precision, 1PPS outputs from ECLKOUT (Pin 97).
Note) These values are not guaranteed, depending on the conditions.
Radio
Total Gain (typ.):
100dB
Noise figure (typ.):
8dB
Synthesizer phase noise (typ.):
–70dBc/Hz (10kHz)
–80dBc/Hz (100kHz)
PLL spurious (typ.):
–45dBc (inside fosc
±
1.023MHz)
–55dBc (outside fosc
±
1.023MHz)
Note) These values are not guaranteed.
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CXD2951GL-4
System Block Diagram
1575.42MHz
TCXO
LNA
CPU
Freq.
Synthesizer
RF/IF
1575.42MHz
→
1.023MHz
BPF
SAW
TCXO
Reference clock
18.414MHz
(GPS, Sony standard)
LNA
Down
Converter
1.023MHz
LPF
1 bit
Acquisition Block
•
Acquire GPS signals
Tracking Block
•
Locking to GPS signals
•
12ch correlations
Costas Loop & DLL
Computation
& Control
•
Control Acquisition
& Tracking block
•
Position calculating
ARM7TDMI
I/O
UART
A/D
RTC
Timer
3ch
RAM
72KB
ROM
288KB
X'tal
32.768kHz
-4-
CXD2951GL-4
Pin Configuration
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
40
A
RFSUB
42
NRING
NC
34
LPFIF
31
V
DD
PLL
32
V
SS
PLL
26
TCK
22
TDO
18
CV
SS
1
14
IOV
SS
1
12
9
6
3
1
A
173
ERXD0
EPORT11 EPORT8
EPORT5 EPORT2 EPORT0
46
B
48
C
MIXGND
44
43
35
LPFRF
33
30
28
TMS
24
TDI
20
TRST
16
11
8
5
EPORT4
2
EPORT1
176
IOV
DD
6
MIXGND MIXGND RFRREF
V
DD
CP RADIOSUB
ETCXO EPORT10 EPORT7
B
47
RFIN
45
41
39
VCODE
CAP
37
V
DD
VCO
36
V
SS
CP
27
ETEST
TCK
23
ETEST
TDO
21
ETEST
TINT
17
13
10
7
4
NC
175
IOV
SS
7
LNASRC LNAMAT
EXTCXO EPORT12 EPORT9
EPORT6 EPORT3
C
50
D
49
55
TEST
OUTD
38
V
SS
VCO
29
ETEST
TMS
25
ETEST
TDI
19
CV
DD
1
15
IOV
DD
1
NC
172
CV
DD
6
171
CV
SS
6
MIXGND LNASRC
D
56
E
IF1V
CC
52
51
174
ETXD0
169
ED1
167
ED3
TESTINN TESTINP
E
58
F
IF2V
CC
54
TEST
OUTN
53
TEST
OUTP
170
ED0
165
ED5
163
ED7
F
G
57
IF1GND
59
IF2GND
60
VCOM
61
RREF
168
ED2
166
ED4
161
ED9
159
ED11
G
H
62
CV
SS
2
64
65
66
164
ED6
162
ED8
157
ED13
155
ED15
ETEST0 ETEST1 ETEST2
H
J
63
CV
DD
2
68
EA18
67
EA19
69
EA17
160
ED10
158
ED12
154
IOV
DD
5
153
IOV
SS
6
J
K
70
EA16
72
EA14
71
EA15
73
EA13
156
ED14
148
152
151
ED16 ETESTXRS EXRS
K
L
75
IOV
SS
2
74
EA12
77
EA11
NC
146
ED18
144
ED20
150
CV
DD
5
NC
L
M
76
IOV
DD
2
79
EA9
NC
142
ED22
147
ED17
149
CV
SS
5
M
N
81
CV
SS
3
83
EA7
78
EA10
140
ED24
143
ED21
145
ED19
N
P
82
CV
DD
3
85
EA5
80
EA8
105
EVIN2
108
110
112
IOV
DD
7
122
ECLKS2
138
ED26
139
ED25
141
ED23
P
EAVDAD ETEST3
R
88
EA2
87
EA3
90
EA0
94
ECLKO
98
102
103
EVIN0
106
EVIN3
111
ETEST4
NC
121
120
126
EXOE
128
EXWE2
136
ED28
135
ED29
137
ED27
R
EXROMI EADVRB
ECLKS1 ECLKS0
T
86
EA4
84
EA6
92
CV
DD
4
93
97
100
104
EVIN1
109
IOV
SS
8
114
116
118
125
124
EXCS0
130
EXWE0
134
ED30
132
IOV
DD
4
133
ED31
T
ECLKI ECLKOUT EAVDPLL
BKUPCV
DD
ECCKO BKUPIOV
DD
EXCS1
U
89
EA1
91
CV
SS
4
95
IOV
SS
3
96
99
101
107
113
115
117
119
123
127
EXWE3
129
EXWE1
131
IOV
SS
5
U
IOV
DD
3 EAVSPLL EAVSAD EADVRT BKUPCV
SS
ECCKI BKUPIOV
SS
EOSCEN IOV
SS
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
: Pin 1 index.
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