88K8483BRI datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Microcontrollers and processors> 88K8483BRI

88K8483BRI: DescriptionMicroprocessor Circuit, PBGA672, ROHS COMPLIANT, FCBG-672; CategoryMicrocontrollers and processors; File Size2MB，162 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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88K8483BRI Overview

Microprocessor Circuit, PBGA672, ROHS COMPLIANT, FCBG-672

88K8483BRI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	ROHS COMPLIANT, FCBG-672
Contacts	672
Reach Compliance Code	not_compliant
ECCN code	5A991
Is Samacsys	N
JESD-30 code	S-PBGA-B672
JESD-609 code	e1
length	27 mm
Humidity sensitivity level	4
Number of terminals	672
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA672,26X26,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	260
power supply	1.2,1.5,2.5,3.3 V
Certification status	Not Qualified
Maximum seat height	3.22 mm
Maximum supply voltage	1.32 V
Minimum supply voltage	1.08 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	27 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR CIRCUIT
Base Number Matches	1

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SPI-4 Exchange

Document Issue 1.0

IDT88K8483

Description

The IDT88K8483 is a 3-port SPI-4 Exchange device. The IDT SPI-4

Exchange devices build on IDT’s proven SPI-4 implementation and

packet fragment processor (PFP) design. The IDT88K8483 suits appli-

cations with slow backpressure response and other advanced

networking applications when there is the need for duplicate ports to re-

route data multiple times through the packet-exchange and temporary

storage for complete in-flight packets.

The data on each SPI-4 interface logical port (LP) are mapped to a

logical identifier (LID). A data flow between logical port addresses on the

various interfaces is accomplished using LID maps that can be dynami-

cally reconfigured. The device enables the connection of two SPI-4

devices to a network processor having one or more SPI-4 interfaces. Up

to 18Mbit of additional buffer memory can be provided using the QDRII

interface. Alternatively, the HSTL I/O may be used to provide a generic

packet interface to a FPGA. The device supports a maximum of 128

logical ports.

Features

Functionality

– Multiplexes logical ports (LPs) from SPI-4A and SPI-4B to SPI-

– Optionally converts between interleaved packet transfers and

whole packet transfers per logical port

– Data redirection per LP between SPI-4A, SPI-4B and 10G

FPGA

– Per LP configurable memory allocation

– Per LP memory expansion via QDR-II SRAM interface

– 3 separate clock generators allowing fully flexible, fully inte-

grated clock derivations and generation

◆

Standard Interfaces

– Two OIF SPI-4 phase 2: 80 - 450 MHz, 256 address range, 64

concurrently active LPs per interface

– One OIF SPI-4 phase 2: 80 - 450 MHz, 256 address range,

128 concurrently active LPs

– SPI-4 FIFO status channel options:

– LVDS full-rate, LVDS quarter-rate, LVTTL quarter-rate

– SPI-4 compatible with Network Processor Streaming Interface

(NPSI NPE-Framer mode of operation)

– HSTL Interface with selectable operating mode

160 - 200 MHz DDR packet interface, 64 concurrently active

LPs; or

QDR-II memory interface: 160 - 200MHz HSTL

– Serial or parallel microprocessor interface for control and

monitoring

– IEEE 1491.1 JTAG

◆

Applications

–

Ethernet transport

SONET / SDH packet transport line cards

Broadband aggregation

Multi-service switches

IP services equipment

Security firewalls

Block Diagram

Auxiliary

10Gbps

Interface

QDR-II 10Gbps

Memory int.

10Gbps FPGA

Packet Int.

Serial / 8bit

MicroprocessorInterface

Micro.

Int.

Tributary

SPI-4s

SPI-4A

64 Logical

Ports

Packet Fragment

Processor A-TM (PFP)

Packet Fragment

Processor A-MT (PFP)

Packet Fragment

Processor B-TM (PFP)

Packet Fragment

Processor B-MT (PFP)

JTAG Interface

Figure 1 IDT88K8483 Block Diagram

SPI-4M

128 Logical

Ports

Main

SPI-4

SPI-4B

64 Logical

Ports

JTAG Int.

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.

1 of 162

2006 Integrated Device Technology, Inc.

October 20, 2006

DSC 6214/-

IDT IDT88K8483

Table Of Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Description Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

SPI-4 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Insert and Extract paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Packet Fragment Processor (PFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

QDR-II Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Generic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Embedded Processor Download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

PMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Direct Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Indirect Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Electrical and Thermal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

2 of 162

October 20, 2006

IDT IDT88K8483

List of Figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Figure 29.

Figure 30.

Figure 31.

Figure 32.

Figure 33.

Figure 34.

Figure 35.

Figure 36.

Figure 37.

Figure 38.

Figure 39.

Figure 40.

Figure 41.

Figure 42.

Figure 43.

Figure 44.

Figure 45.

Figure 46.

Figure 47.

Figure 48.

Figure 49.

Figure 50.

Figure 51.

Figure 52.

Figure 53.

IDT88K8483 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PFP Structure Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PFP Allocation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

QDR-II SRAM Structure Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

QDR-II Allocation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SPI-4 Ingress Port Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

SPI-4 Egress Calendar Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SPI-4 Tributary to SPI-4 Main Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SPI-4 main to SPI-4 Tributary Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

PFP Loop Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Microprocessor, Auxiliary and Internal Traffic Detector/Generator Data Path . . . . . . . 38

PFP Redirect Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

IDT88K8483 SPI-4 Connections Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

SPI-4 Ingress Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

SPI-4 Ingress State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

SPI-4 Egress State Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Egress word transition state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Status Channel State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

PFP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

PFP Ingress Flow Control Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

PFP Flow Control Example For Over Booking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 54

IDT88K8483 and IDT7172604 QDR-II SRAM connections . . . . . . . . . . . . . . . . . . . . . 55

Flow Control Mode 1 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

QDR-II FIFOs Allocation Example For Buffering Option . . . . . . . . . . . . . . . . . . . . . . . 57

QDR-II Flow Control Example For Buffering Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Flow Control Mode 2 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

IDT88K8483 and FPGA connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Generic Interface - Transfer Format for Normal Data . . . . . . . . . . . . . . . . . . . . . . . . . 59

Generic Interface - Transfer Format for Stratus Word. . . . . . . . . . . . . . . . . . . . . . . . . . 60

Microprocessor Interface - Parallel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Interrupt Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

PMON Measure Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Internal PMON Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

External PMON Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Clock Generator Type M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Clock Generator Type T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Power-on-Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

JTAG Daisy Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

TRSTB Signal During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

IDT88K8483 Power Supply Generation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

IDT88K8483 VDDA25 Filter Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

IDT88K8483 SPI4x_VREF Filter Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Indirect Register Access Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Indirect access module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Auxiliary Interface - QDR-II / Generic - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . 154

Auxiliary Interface - QDR-II / Generic - Read Access . . . . . . . . . . . . . . . . . . . . . . . . 154

MCU Interface - Motorola Mode - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

MCU Interface - Motorola Mode - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

MCU Interface - Intel Mode - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

MCU Interface - Intel Mode - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

88K8483 Top View Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

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IDT IDT88K8483

List of Tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Table 47.

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

IDT88K8483 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

SPI-4 Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Generic Interface - Control Field Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Field Associated Non-Critical Event List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Field Associated Critical Event List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Non Field Associated Event List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Time Base Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

CLK_SEL signals configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

DIV4 signal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

JTAG Instruction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

JTAG ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Direct Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Indirect Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Direct Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Indirect Registers Map - Segment Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Indirect Registers Map - Module Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Indirect Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Global Software Reset Register (Register Offset=0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Microprocessor Mailbox Input FIFO Data Register (Register Offset=0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Microprocessor Mailbox Input FIFO Length Register (Register Offset=0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Microprocessor Mailbox Input FIFO Status Register (Register Offset=0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Microprocessor Mailbox Output FIFO Data Register (Register Offset=0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Microprocessor Mailbox Output FIFO Length Register (Register Offset=0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Microprocessor Mailbox Input FIFO Status Register (Register Offset=0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Embedded Processor State Register (Register Offset=0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Microprocessor Indirect Access Control Register (Register Offset=0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Microprocessor Indirect Access Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Microprocessor Indirect Access Data Register -1 (Register Offset=0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Microprocessor Indirect Access Data Register - 2 (Register Offset=0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Microprocessor Indirect Access Data Register - 3 (Register Offset=0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Microprocessor Indirect Access Data Register - 4 (Register Offset=0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Microprocessor Indirect Access Address Register - 1 (Register Offset=0x1F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Microprocessor Indirect Access Address Register - 2 (Register Offset=0x20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Microprocessor Indirect Access Address Register - 3 (Register Offset=0x21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

PFP T-M insert control register (Register Offset=0x0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

PFP T-M insert data register(Register Offset=0x1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

PFP T-M extract control register (Register Offset=0x2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

PFP T-M extract data register (Register Offset=0x3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

PFP M-T insert control register (Register Offset=0x4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

PFP M-T insert data register (Register Offset=0x5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

PFP M-T extract control register (Register Offset=0x6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

PFP M-T extract data register (Register Offset=0x7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Primary Interrupt Indication Register (Register Offset=0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Primary Interrupt Enable Register (Register Offset=0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Secondary Module Indication Register (Register Offset=0x0A.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Secondary Module Enable Register (Register Offset=0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Secondary interrupt module B Indication register(Register Offset=0xC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Secondary Interrupt module B enable register (Register Offset=0xD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Interrupt secondary COMMON indication register (Register Offset=0xe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

Interrupt Secondary COMMON Enable Register (register_offset=0xf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

MCLK Divider Sticky Register (Block Base=0x0a00, Register Offset=0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Clock Control Input Status Register (Block Base=0x0a00, Register Offset=0x01) . . . . . . . . . . . . . . . . . . . . . . . . . .104

5 of 162

October 20, 2006

88K8483BRI Related Products

	88K8483BRI	IDT88K8483BRI	IDT88K8483BLI
Description	Microprocessor Circuit, PBGA672, ROHS COMPLIANT, FCBG-672	Microprocessor Circuit, PBGA672, ROHS COMPLIANT, FCBG-672	Microprocessor Circuit, PBGA672, FCBG-672
Is it lead-free?	Lead free	Lead free	Contains lead
Is it Rohs certified?	conform to	conform to	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	BGA	BGA	BGA
package instruction	ROHS COMPLIANT, FCBG-672	ROHS COMPLIANT, FCBG-672	BGA, BGA672,26X26,40
Contacts	672	672	672
Reach Compliance Code	not_compliant	not_compliant	not_compliant
JESD-30 code	S-PBGA-B672	S-PBGA-B672	S-PBGA-B672
JESD-609 code	e1	e1	e0
length	27 mm	27 mm	27 mm
Number of terminals	672	672	672
Maximum operating temperature	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA
Encapsulate equivalent code	BGA672,26X26,40	BGA672,26X26,40	BGA672,26X26,40
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	260	260	225
power supply	1.2,1.5,2.5,3.3 V	1.2,1.5,2.5,3.3 V	1.2,1.5,2.5,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.22 mm	3.22 mm	3.22 mm
Maximum supply voltage	1.32 V	1.32 V	1.32 V
Minimum supply voltage	1.08 V	1.08 V	1.08 V
Nominal supply voltage	1.2 V	1.2 V	1.2 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	30	30
width	27 mm	27 mm	27 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR CIRCUIT	MICROPROCESSOR CIRCUIT	MICROPROCESSOR CIRCUIT
Is Samacsys	N	N	-
Humidity sensitivity level	4	4	-
Base Number Matches	1	1	-

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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