82845 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Microcontrollers and processors> 82845

82845: DescriptionMultifunction Peripheral, CMOS, 37.50 X 37.50 MM, FCBGA-593; CategoryMicrocontrollers and processors; File Size1MB，150 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

Download Datasheet Parametric View All

82845 Overview

Multifunction Peripheral, CMOS, 37.50 X 37.50 MM, FCBGA-593

82845 Parametric

Parameter Name	Attribute value
Maker	Intel
Parts packaging code	BGA
package instruction	37.50 X 37.50 MM, FCBGA-593
Contacts	593
Reach Compliance Code	compliant
Is Samacsys	N
Address bus width	32
boundary scan	NO
Bus compatibility	PENTIUM 4
maximum clock frequency	100 MHz
External data bus width	64
JESD-30 code	S-XBGA-B593
length	37.5 mm
Number of terminals	593
Package body material	UNSPECIFIED
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	1.9 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	37.5 mm
Base Number Matches	1

Preview

Download Datasheet

View All

Intel 845 Chipset: 82845

Memory Controller Hub (MCH)

Datasheet

September 2001

Document Number:

290725-001

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

845 chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

I C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I C bus/protocol and was developed by Intel.

Implementations of the I

C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips

Corporation.

Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporation

www.intel.com

or call 1-800-548-4725

Intel , Pentium and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other

countries.

*Other names and brands may be claimed as the property of others.

Intel 82845 MCH Datasheet

Contents

Introduction ........................................................................................................................11

1.1

1.2

1.3

1.4

Terminology and Notations ...................................................................................11

Reference Documents ..........................................................................................13

Intel 845 Chipset System Architecture ................................................................14

Intel 82845 MCH Overview .................................................................................14

1.4.1

System Bus Interface ............................................................................15

1.4.2

System Bus Error Checking ..................................................................15

1.4.3

System Memory Interface .....................................................................16

1.4.4

AGP Interface........................................................................................16

1.4.5

Hub Interface.........................................................................................17

1.4.6

Intel MCH Clocking ..............................................................................17

1.4.7

System Interrupts ..................................................................................18

1.4.8

Powerdown Flow ...................................................................................18

System Bus Signals ..............................................................................................21

SDR SDRAM Interface Signals.............................................................................23

Hub Interface Signals............................................................................................23

AGP Interface Signals...........................................................................................24

2.4.1

AGP Addressing Signals .......................................................................24

2.4.2

AGP Flow Control Signals .....................................................................25

2.4.3

AGP Status Signals ...............................................................................25

2.4.4

AGP Strobes Signals.............................................................................26

2.4.5

AGP/PCI Signals ...................................................................................26

Clocks, Reset, and Miscellaneous Signals ...........................................................28

Voltage Reference and Power Signals .................................................................29

Reset States During Reset ...................................................................................30

Signal Description..............................................................................................................19

2.1

2.2

2.3

2.4

2.5

2.6

2.7

Register Description ..........................................................................................................31

3.1

3.2

PCI Bus Configuration Space Access...................................................................32

3.2.1

Standard PCI Bus Configuration Mechanism........................................33

3.2.2

Routing Configuration Accesses ...........................................................33

I/O Mapped Registers ...........................................................................................34

3.3.1

CONF_ADDR—Configuration Address Register ..................................34

3.3.2

CONF_DATA—Configuration Data Register.........................................36

Memory-Mapped Register Space .........................................................................36

3.4.1

DRAMWIDTH—DRAM Width Register.................................................37

3.4.2

DQCMDSTR—Strength Control Register (SDQ and

CMD Signal Groups) .............................................................................38

3.4.3

CKESTR—Strength Control Register (SCKE Signal Group) ................39

3.4.4

CSBSTR—Strength Control Register (SCS# Signal Group).................40

3.4.5

CKSTR—Strength Control Register (Clock Signal Group) ...................41

3.4.6

RCVENSTR—Strength Control Register (RCVENOUT

Signal Group) ........................................................................................42

3.3

3.4

Intel 82845 MCH Datasheet

3.5

3.6

Host-Hub Interface Bridge Device Registers (Device 0)......................................43

3.5.1

VID—Vendor Identification Register (Device 0) ....................................45

3.5.2

DID—Device Identification Register (Device 0).....................................45

3.5.3

PCICMD—PCI Command Register (Device 0) .....................................46

3.5.4

PCISTS—PCI Status Register (Device 0).............................................47

3.5.5

RID—Revision Identification Register (Device 0)..................................48

3.5.6

SUBC—Sub-Class Code Register (Device 0).......................................48

3.5.7

BCC—Base Class Code Register (Device 0)........................................48

3.5.8

MLT—Master Latency Timer Register (Device 0) .................................49

3.5.9

HDR—Header Type Register (Device 0) ..............................................49

3.5.10 APBASE—Aperture Base Configuration Register (Device 0) ...............50

3.5.11 SVID—Subsystem Vendor Identification (Device 0) .............................51

3.5.12 SID—Subsystem Identification (Device 0) ............................................51

3.5.13 CAPPTR—Capabilities Pointer (Device 0) ............................................51

3.5.14 DWTC—DRAM Write Thermal Management Control

3.5.15 AGPM—AGP Miscellaneous Configuration Register (Device 0)...........53

3.5.16 DRTC—DRAM Read Thermal Management Control

3.5.17 DRB[0:7]—DRAM Row Boundary Registers (Device 0)........................55

3.5.18 DRA—DRAM Row Attribute Registers (Device 0) ................................56

3.5.19 DRT—DRAM Timing Register (Device 0) .............................................58

3.5.20 DRC—DRAM Controller Mode Register (Device 0) ..............................59

3.5.21 DERRSYN—DRAM Error Syndrome Register (Device 0) ....................61

3.5.22 EAP—Error Address Pointer Register (Device 0) .................................61

3.5.23 PAM[0:6]—Programmable Attribute Map Registers (Device 0) ...........62

3.5.24 FDHC—Fixed DRAM Hole Control Register (Device 0)........................65

3.5.25 SMRAM—System Management RAM Control Register (Device 0) ......66

3.5.26 ESMRAMC—Extended System Mgmt RAM Control

3.5.27 ACAPID—AGP Capability Identifier Register (Device 0).......................68

3.5.28 AGPSTAT—AGP Status Register (Device 0) .......................................69

3.5.29 AGPCMD—AGP Command Register (Device 0)..................................70

3.5.30 AGPCTRL—AGP Control Register (Device 0)......................................71

3.5.31 APSIZE—Aperture Size (Device 0) .......................................................72

3.5.32 ATTBASE—Aperture Translation Table Base Register (Device 0).......73

3.5.33 AMTT—AGP Interface Multi-Transaction Timer Register (Device 0) ...74

3.5.34 LPTT—AGP Low Priority Transaction Timer Register (Device 0).........75

3.5.35 TOM—Top of Low Memory Register (Device 0) ...................................76

3.5.36 MCHCFG—MCH Configuration Register (Device 0).............................77

3.5.37 ERRSTS—Error Status Register (Device 0) .........................................78

3.5.38 ERRCMD—Error Command Register (Device 0) .................................79

3.5.39 SMICMD—SMI Command Register (Device 0) ....................................81

3.5.40 SCICMD—SCI Command Register (Device 0) .....................................81

3.5.41 SKPD—Scratchpad Data Register (Device 0) ......................................82

3.5.42 CAPID—Product Specific Capability Identifier Register (Device 0) ......82

Bridge Registers (Device 1) ..................................................................................83

3.6.1

VID1—Vendor Identification Register (Device 1) ..................................84

3.6.2

DID1—Device Identification Register (Device 1)...................................84

3.6.3

PCICMD1—PCI-PCI Command Register (Device 1)............................85

3.6.4

PCISTS1—PCI-PCI Status Register (Device 1)....................................86

3.6.5

RID1—Revision Identification Register (Device 1)................................87

3.6.6

SUBC1—Sub-Class Code Register (Device 1).....................................87

Intel 82845 MCH Datasheet

3.6.7

3.6.8

3.6.9

3.6.10

3.6.11

3.6.12

3.6.13

3.6.14

3.6.15

3.6.16

3.6.17

3.6.18

3.6.19

3.6.20

3.6.21

3.6.22

4.1

BCC1—Base Class Code Register (Device 1)......................................87

MLT1—Master Latency Timer Register (Device 1) ...............................88

HDR1—Header Type Register (Device 1) ............................................88

PBUSN1—Primary Bus Number Register (Device 1) ...........................88

SBUSN1—Secondary Bus Number Register (Device 1) ......................89

SUBUSN1—Subordinate Bus Number Register (Device 1)..................89

SMLT1—Secondary Master Latency Timer Register (Device 1) .........90

IOBASE1—I/O Base Address Register (Device 1) ...............................91

IOLIMIT1—I/O Limit Address Register (Device 1) ................................91

SSTS1—Secondary PCI-PCI Status Register (Device 1) .....................92

MBASE1—Memory Base Address Register (Device 1) ........................93

MLIMIT1—Memory Limit Address Register (Device 1) .........................93

PMBASE1—Prefetchable Memory Base Address

PMLIMIT1—Prefetchable Memory Limit Address

BCTRL1—PCI-PCI Bridge Control Register (Device 1) ........................96

ERRCMD1—Error Command Register (Device 1) ...............................97

System Address Map.........................................................................................................99

Memory Address Ranges .....................................................................................99

4.1.1

VGA and MDA Memory Space............................................................101

4.1.2

PAM Memory Spaces..........................................................................102

4.1.3

ISA Hole Memory Space .....................................................................102

4.1.4

TSEG SMM Memory Space ................................................................103

4.1.5

IOAPIC Memory Space .......................................................................103

4.1.6

System Bus Interrupt APIC Memory Space ........................................103

4.1.7

High SMM Memory Space...................................................................103

4.1.8

AGP Aperture Space (Device 0 BAR) .................................................104

4.1.9

AGP Memory and Prefetchable Memory.............................................104

4.1.10 Hub Interface Subtractive Decode ......................................................104

AGP Memory Address Ranges...........................................................................104

4.2.1

AGP DRAM Graphics Aperture ...........................................................105

System Management Mode (SMM) Memory Range...........................................105

4.3.1

SMM Space Definition .........................................................................106

4.3.2

SMM Space Restrictions .....................................................................106

I/O Address Space..............................................................................................107

Intel MCH Decode Rules and Cross-Bridge Address Mapping.........................107

4.5.1

Hub Interface Decode Rules ...............................................................107

4.5.2

AGP Interface Decode Rules ..............................................................108

System Bus .........................................................................................................109

5.1.1

Dynamic Bus Inversion........................................................................109

5.1.2

System Bus Interrupt Delivery .............................................................110

5.1.3

Upstream Interrupt Messages .............................................................110

System Memory Interface ...................................................................................110

5.2.1

SDR SDRAM Interface Overview........................................................110

5.2.2

Memory Organization and Configuration.............................................111

5.2.2.1

Configuration Mechanism For DIMMs ...............................111

5.2.2.1.1

Memory Detection and Initialization ...................111

5.2.2.1.2

SMBus Configuration and Access of the

Serial Presence Detect Ports .............................112

4.2

4.3

4.4

4.5

Functional Description .....................................................................................................109

5.1

5.2

Intel 82845 MCH Datasheet

Recommended Resources

Digital camera flash control circuit

Internal cubic block diagram of switching power supply integrated circuit 5M0269R

Metal detector circuit diagram

Triac circuit with non-sensitive gate inductive load

Automatic recording telephone interface circuit diagram

Three-tube astable circuit (1)

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components