Operating Junction Temperature Range (TJ) .......-55°C to +150°C
Storage Ambient Temperature Range (TS)...........-55°C to +150°C
Lead Temperature (soldering, 10s)......................................+300°C
Soldering Temperature (reflow)............................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +2.97V to +3.63V, CML output load is 50Ω to V
CC
, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V and T
A
= +25°C,
unless otherwise specified.) (Note 1)
PARAMETER
POWER SUPPLY
MAX3747A including the CML output current
MAX3747B including the CML output current
Supply Current (Note 2)
I
CC
MAX3747A excluding the CML output
current
MAX3747B excluding the CML output
current
Power-Supply Noise Rejection
INPUT SPECIFICATION
Input Sensitivity
Input Overload
OUTPUT SPECIFICATION
Output Resistance
Differential Output Return Loss
CML Differential Output Voltage
Differential Output Signal When
Disabled
Data-Output Transition Time
TRANSFER CHARACTERISTIC
K28.5 pattern at 3.2Gbps
PRBS 2
23
- 1 equivalent pattern at 2.7Gbps
(Note 6)
Deterministic Jitter (Notes 4, 5)
DJ
K28.5 pattern at 2.1Gbps
PRBS 2
23
- 1 equivalent pattern at 155Mbps
(Note 6)
Random Jitter
V
IN
= 4mV
P-P
(Notes 4, 7)
13.2
14
12
85
3.5
19
25
17
150
5
ps
RMS
ps
P-P
R
OUT
(Note 4)
DUT is powered on, f < 3GHz
MAX3747A/MAX3747B
4mV
P-P
≤
V
IN
≤
1200mV
P-P
AC-coupled outputs, V
IN-MAX
applied to the
input (Note 4)
20% to 80% (Note 4)
70
600
42
50
15
800
1000
58
Ω
dB
mV
P-P
mV
P-P
ps
V
IN-MIN
V
IN-MAX
(Note 3)
(Note 3)
1200
4
mV
P-P
mV
P-P
PSNR
f < 2MHz
36
38
18
20
30
41
43
24
26
dB
mA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
15
120
2
Maxim Integrated
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +2.97V to +3.63V, CML output load is 50Ω to V
CC
, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V and T
A
= +25°C,
unless otherwise specified.) (Note 1)
PARAMETER
Input-Referred Noise
Low-Frequency Cutoff
LOS Hysteresis
LOS Assert/Deassert Time
Low LOS Assert Level
Low LOS Deassert Level
Medium LOS Assert Level
Medium LOS Deassert Level
High LOS Assert Level
High LOS Deassert Level
TTL/CMOS I/O
V
REF
Voltage
LOS Output High Voltage
LOS Output Low Voltage
DISABLE Input High
DISABLE Input Low
DISABLE Input Current
V
REF
V
OH
V
OL
V
IH
V
IL
R
LOS
= 4.7kΩ to 10kΩ to V
CC_HOST
R
LOS
= 4.7kΩ to 10kΩ to V
CC_HOST
(3V)
R
LOS
= 4.7kΩ to 10kΩ to V
CC_HOST
(3.6V)
2.0
0.8
10
V
CC
-
1.35
2.4
0.4
V
CC
-
1.3V
V
CC
-
1.19
V
V
V
V
V
µA
10log(V
DEASSERT
/ V
ASSERT
) (Note 4)
MAX3747A (Notes 4, 8)
MAX3747B (Notes 4, 8, 9)
V
TH
= -1.3V (Notes 4, 10)
V
TH
= -1.3V (Notes 4, 10)
V
TH
= -0.68V (Notes 4, 10)
V
TH
= -0.68V (Notes 4, 10)
V
TH
= -0.114V (Notes 4, 10)
V
TH
= -0.114V (Notes 4, 10)
36.0
22.0
1.25
2.3
2.5
4.1
6.2
29.0
44.8
53.7
86.0
40.0
5.9
9.3
36.0
62.0
63.6
115
SYMBOL
CONDITIONS
V
IN
= 4mV
P-P
(Note 4)
MIN
TYP
120
6.4
MAX
150
UNITS
µV
RMS
kHz
dB
µs
mV
P-P
mV
P-P
mV
P-P
mV
P-P
mV
P-P
mV
P-P
The data-input transition time is controlled by a 4th-order Bessel filter with f
-3dB
= 0.75 x 2.667GHz for all data rates of
2.667Gbps and below. The f
-3db
= 0.75 x 3.2GHz for a data rate of 3.2Gbps.
Note 2:
Supply current is measured with unterminated outputs or with AC-coupled output termination (see Figure 1).
Note 3:
Between sensitivity and overload, all AC specifications are met and the output is 0.95 x limited output amplitude.
Note 4:
Guaranteed by design and characterization.
Note 5:
The deterministic jitter (DJ) caused by the input filter is not included in the DJ generation specification.
Note 6:
The PRBS 2
23
- 1 equivalent pattern consists of a K28.5 pattern plus 240 ones plus K28.5 pattern plus 240 zeros.
Note 7:
Random jitter was measured without using a filter at the input.
Note 8:
The signal at the input is switched between two amplitudes, Signal_ON and Signal_OFF, as shown in Figure 2A.
Note 9:
The signal at the input is switched between 1.2V
P-P
and Signal_OFF as shown in Figure 2B.
Note 10:
V
TH
is the voltage at pin 5 referenced to V
CC
(see Figure 5).
Note 1:
Maxim Integrated
3
MAX3747A/MAX3747B
155Mbps to 3.2Gbps, Low-Power SFP
Limiting Amplifiers
V
CC
I
CC
(SUPPLY
CURRENT)
I
OUT
(CML OUTPUT
CURRENT)
50
I
50
I
MAX3747A
MAX3747B
Figure 1. Power-Supply Current Measurement
V
IN
V
IN
SIGNAL_ON = 1.2V
P-P
(OVERLOAD)
SIGNAL_ON
1dB
MAXIMUM DEASSERT LEVEL FOR A GIVEN V
TH
MAXIMUM DEASSERT LEVEL FOR A GIVEN R
TH1
/R
TH2
RATIO
6dB
MAXIMUM POWER-DETECT WINDOW
MINIMUM ASSERT LEVEL FOR A GIVEN V
TH
6dB
MAXIMUM POWER-DETECT WINDOW
MINIMUM ASSERT LEVEL FOR A GIVEN R
TH1
/R
TH2
RATIO
0V
SIGNAL_OFF
TIME
0V
SIGNAL_OFF
TIME
Figure 2A. LOS Deassert Threshold—Set 1dB Below Receiver
Sensitivity
Figure 2B. LOS Deassert Threshold—Operating at Input
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