8-Bit Programmable 2- to 5-Phase
Synchronous Buck Controller
ADP3189
FEATURES
Selectable 2-, 3-, 4-, or 5-phase operation at up
to 1 MHz per phase
±7.7 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to external
high-power drivers
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly
VID code changes
Digitally programmable 0.5 V to 1.6 V output— supports
both VR10.x and VR11 specifications
Programmable short-circuit protection with programmable
latch-off delay
This device uses a multi-mode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The phase relation-
ship of the output signals can be programmed to provide 2-, 3-,
4-, or 5-phase operation, allowing for the construction of up to
five complementary buck switching stages.
The ADP3189 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current, so it is optimally positioned for a system transient.
The ADP3189 also provides accurate and reliable short-circuit
protection, adjustable current limiting, and a delayed power
good output that accommodates on-the-fly output voltage
changes requested by the CPU.
ADP3189 is specified over the extended commercial tem-
perature range of 0°C to +85°C and is available in a
40-lead LFCSP package.
1
APPLICATIONS
Desktop PC power supplies for
Next generation Intel® processors
VRM modules
Protected by U.S. Patent Number 6,683,441; others pending.
GENERAL DESCRIPTION
The ADP3189
1
is a highly efficient multi-phase synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. It uses an internal 8-bit DAC to
read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between 0.5 V
and 1.6 V.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.
ADP3189
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Test Circuits....................................................................................... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function DescriptionS ............................ 9
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 12
Start-Up Sequence...................................................................... 12
Phase Detection Sequence......................................................... 12
Master Clock Frequency............................................................ 13
Output Voltage Differential Sensing ........................................ 13
Output Current Sensing ............................................................ 13
Active Impedance Control Mode............................................. 13
Current Control Mode and Thermal Balance ........................ 13
Voltage Control Mode................................................................ 14
Delay Timer................................................................................. 14
Soft Start ...................................................................................... 14
Current Limit, Short Circuit, and Latch-Off Protection....... 15
Dynamic VID.............................................................................. 15
Power Good Monitoring ........................................................... 15
Output Crowbar ......................................................................... 16
Output Enable and UVLO ........................................................ 16
Thermal Monitoring .................................................................. 16
Application Information................................................................ 22
Setting the Clock Frequency ..................................................... 22
Soft Start Delay Time ................................................................. 22
Current Limit Latch-Off Delay Times..................................... 22
Inductor Selection ...................................................................... 23
Designing an Inductor............................................................... 23
Selecting a Standard Inductor .............................................. 23
Current Sense Amplifier............................................................ 24
Inductor DCR Temperature Correction ................................. 24
Load Line Setting........................................................................ 25
Output Offset .............................................................................. 26
C
OUT
Selection ............................................................................. 26
Power MOSFETs......................................................................... 27
Ramp Resistor Selection............................................................ 28
COMP Pin Ramp ....................................................................... 28
Current Limit SetPoint .............................................................. 29
Feedback Loop Compensation Design.................................... 29
C
IN
Selection and Input Current di/dt Reduction.................. 31
Thermal Monitor Design .......................................................... 31
Tuning the ADP3189 ................................................................. 32
DC Loadline Setting .............................................................. 32
AC Loadline Setting............................................................... 33
Initial Transient Setting ......................................................... 33
Layout and Component Placement ......................................... 34
General Recommendations .................................................. 34
Power Circuitry Recommendations .................................... 34
Signal Circuitry Recommendations .................................... 34
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
REVISION HISTORY
7/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADP3189
FUNCTIONAL BLOCK DIAGRAM
VCC
31
RT
12
RAMPADJ
13
ADP3189
UVLO
SHUTDOWN
AND BIAS
OSCILLATOR
SET
EN
19
OD
GND
18
CMP
RESET
30
PWM1
850mV
EN
1
DAC + 150mV
CSREF
CURRENT
BALANCING
CIRCUIT
CMP
RESET
2-/3-/4-/5-PHASE
DRIVER LOGIC
29
PWM2
CMP
RESET
28
PWM3
CMP
DAC – 250mV
CMP
PWRGD
2
DELAY
RESET
27
PWM4
RESET
CURRENT
LIMIT
26
PWM5
CROWBAR
25
SW1
TTSENSE
10
VRHOT
9
VRFAN
8
THERMAL
THROTTLING
CONTROL
24
SW2
23
SW3
22
SW4
21
SW5
17
CSCOMP
ILIMIT
11
DELAY
7
CURRENT
LIMIT
CIRCUIT
15
CSREF
16
CSSUM
4
COMP
5
+
FB
PRECISION
REFERENCE
FBRTN
3
14
LLSET
–
BOOT
VOLTAGE
& SOFT-START
CONTROL
6
SS
VIDSEL
40
VID
DAC
05626-001
32
33
34
35
36
37
38
39
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Figure 1.
Rev. 0 | Page 3 of 36
ADP3189
SPECIFICATIONS
VCC = 12 V, FBRTN = GND, T
A
= 0°C to 85°C, unless otherwise noted.
1
Table 1.
Parameter
ERROR AMPLIFIER
Output Voltage Range
2
Accuracy
Symbol
V
COMP
V
FB
Conditions
Min
0.95
Relative to nominal DAC output, referenced to
FBRTN,
LLSET = CSREF, Figure 2,
VIDSEL = GND,
VIDSEL = 1.25 V,
VID Range 1.00625 V to 1.60000 V
In start-up
CSREF − LLSET = 80 mV
VCC = 10 V to 14 V
13.5
FB forced to V
OUT
− 3%
COMP = FB
COMP = FB
Relative to CSREF
C
DELAY
= 10 nF
VIDx, VIDSEL
VIDx, VIDSEL
Typ
Max
3.95
Unit
V
−7.7
−7.7
1.092
−78
−1
1.1
−80
0.003
15
125
500
20
25
+7.7
+7.7
1.108
−82
+1
16.5
200
mV
mV
V
mV
LSB
%
μA
μA
μA
MHz
V/μs
mV
nA
ms
V
V
V
μA
ns
ns
V
FB(BOOT)
Load Line Positioning Accuracy
Differential Non-Linearity
Line Regulation
Input Bias Current
FBRTN Current
Output Current
Gain Bandwidth Product
Slew Rate
LLSET Input Voltage Range
LLSET Input Bias Current
BOOT Voltage Hold Time
VID INPUTS
Input Low Voltage
Input High Voltage
Max V
IH
for VID on Fly
2
Input Current
VID Transition Delay Time
2
No CPU Detection Turn-Off Delay
Time
2
OSCILLATOR
Frequency Range
2
Frequency Variation
ΔV
FB
I
FB
I
FBRTN
I
COMP
GBW
(ERR)
V
LLSET
I
LLSET
t
BOOT
V
IL(VID)
V
IH(VID)
I
IN(VID)
−250
−120
2
+250
+120
0.4
0.8
1.26
−1
VID code change to FB change
VID code change to PWM going low
200
200
f
OSC
f
PHASE
Output Voltage
RAMPADJ Output Voltage
RAMPADJ Input Current Range
CURRENT SENSE AMPLIFIER
Offset Voltage
Input Bias Current
Gain Bandwidth Product
Slew Rate
Input Common-Mode Range
Output Voltage Range
Output Current
Current Limit Latch-Off Delay Time
V
RT
V
RAMPADJ
I
RAMPADJ
V
OS(CSA)
I
BIAS(CSSUM)
GBW
(CSA)
T
A
= 25°C, R
T
= 243 kΩ, 5-phase
T
A
= 25°C, R
T
= 113 kΩ, 5-phase
T
A
= 25°C, R
T
= 51 kΩ, 5-phase
R
T
= 243 kΩ to GND
RAMPADJ − FB
0.25
180
1.6
−50
1
−1.0
−50
200
400
800
1.7
5
220
1.8
+50
50
+1.0
+50
MHz
kHz
kHz
kHz
V
mV
μA
mV
nA
MHz
V/μs
V
V
μA
ms
CSSUM − CSREF, Figure 3
CSSUM = CSCOMP
C
CSCOMP
= 10 pF
CSSUM and CSREF
10
10
0
0.05
500
8
3
2.8
I
CSCOMP
t
OC(DELAY)
C
DELAY
= 10 nF
Rev. 0 | Page 4 of 36
ADP3189
Parameter
CURRENT BALANCE AMPLIFIER
Common Mode Range
Input Resistance
Input Current
Input Current Matching
CURRENT LIMIT COMPARATOR
Output Voltage
Output Current
Maximum Output Current
2
Current Limit Threshold Voltage
Current Limit Setting Ratio
DELAY TIMER
Normal Mode Output Current
Output Current in Current Limit
Threshold Voltage
SOFT START
Output Current
ENABLE INPUT
Threshold Voltage
Hysteresis
Input Current
Delay Time
OD OUTPUT
Output Low Voltage
Output High Voltage
THERMAL THROTTLING CONTROL
TTSENSE Voltage Range
TTSENSE VRFAN Threshold Voltage
TTSENSE VRHOT Threshold Voltage
TTSENSE Hysteresis
TTSENSE Input Current
VRFAN Output Low Voltage
VRHOT Output Low Voltage
POWER GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Low Voltage
Power Good Delay Time
During Soft Start
2
VID Code Changing
VID Code Static
Crowbar Trip Point
Crowbar Reset Point
Crowbar Delay Time
VID Code Changing
VID Code Static
PWM OUTPUTS
Output Low Voltage
Output High Voltage
Symbol
V
SW(X)CM
R
SW(X)
I
SW(X)
ΔI
SW(X)
V
ILIMIT
I
ILIMIT
V
CL
Conditions
Min
−600
35
2.5
−5
1.6
60
105
Typ
Max
+200
65
5.5
+5
1.8
Unit
mV
kΩ
μA
%
V
μA
μA
mV
mV/μA
μA
μA
V
μA
mV
mV
μA
ms
mV
V
5.3
1.14
840
−135
300
300
−300
200
300
V
V
mV
mV
μA
mV
mV
mV
mV
mV
ms
μs
ns
mV
mV
μs
ns
500
mV
V
SWx = 0 V
SWx = 0 V
SWx = 0 V
R
ILIMIT
= 143 kΩ
R
ILIMIT
= 143 kΩ
V
CSREF
− V
CSCOMP
, R
ILIMIT
= 143 kΩ
V
CL
/I
ILIMIT
50
4.0
1.7
12
120
10
15
3.75
1.7
15
850
100
2
100
135
I
DELAY
I
DELAY(CL)
V
DELAY(TH)
I
SS
V
TH(EN)
V
HYS(EN)
I
IN(EN)
t
DELAY(EN)
V
OL(OD)
V
OH(OD)
Internally limited
During start-up
12
3.0
1.6
12
800
80
−1
EN > 950 mV, C
DELAY
= 10 nF
18
4.5
1.8
18
900
120
+1
500
4
0
1.08
780
−105
5
V
OL(VRFAN)
V
OL(VRHOT)
V
PWRGD(UV)
V
PWRGD(OV)
V
OL(PWRGD)
I
VRFAN (SINK)
= −4 mA
I
VRHOT (SINK)
= −4 mA
Relative to nominal DAC output
Relative to nominal DAC output
I
PWRGD(SINK)
= −4 mA
C
DELAY
= 10 nF
100
−200
100
1.11
810
55
−120
150
150
−250
150
150
2
400
200
150
375
400
400
160
5
V
CROWBAR
t
CROWBAR
Relative to nominal DAC output
Relative to FBRTN
Overvoltage to PWM going low
100
320
100
200
430
V
OL(PWM)
V
OH(PWM)
I
PWM(SINK)
= −400 μA
I
PWM(SOURCE)
= 400 μA
4.0
Rev. 0 | Page 5 of 36
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