ZL38005
Enhanced Voice Processor
with Dual Wideband Codecs
Data Sheet
Features
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100 MHz (200 MIPs) Zarlink voice processor with
hardware accelerator.
Dual narrow band (8 KHz)
∆Σ
ADCs with input
buffer gain selection
Dual narrow band (8 KHz)
∆Σ
DACs
Dual function Inter-IC Sound (I
2
S) port
PCM port supports TDM (ST BUS, GCI or McBSP
framing) or SSI modes at bit rates of 128, 256, 512,
1024, 2048, 4096, 8192 or 16384 Kb/sec
Separate slave (microcontroller) and master
(Flash) SPI ports, maximum clock rate = 25 MHz
11 General Purpose Input/Output (GPIO) pins
General purpose UART port
Bootloadable for future Zarlink software upgrades
External oscillator or crystal/ceramic resonator
1.2 V Core; 3.3 V IO with 5 V-tolerant inputs
IEEE-1149.1 compatible JTAG port
*Pb Free Matte Tin
-40°C to +85°C
Ordering Information
ZL38005QCG1
ZL38005GGG2
100 Pin LQFP*
96 Pin CABGA*
Trays, Bake &
Drypack
Trays, Bake &
Drypack
September 2007
Applications
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Hands-free car kits
Full duplex speaker-phone for digital telephone
Echo cancellation for video conferences
Intercom Systems
Security Systems
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Buffer
CODEC[0]
ADC
DAC
Driver
Buffer
CODEC[1]
ADC
DAC
Driver
PCM P0
IRQ
OSCo
APLL
Interrupt
Controller
Instruction
Memory
ROM
DSP
Core
PCM P0
Clock
OSC
OSCi
PCM_CLKi
PCM_LBCi
JTAG
RAM
Timing
Generator
Master
SPI
Hardware
Accelerator
Data RAM
Slave
SPI
UART
GPIO
I
2
S
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006-2007, Zarlink Semiconductor Inc. All Rights Reserved.
ZL38005
1.0
Functional Description
Data Sheet
The ZL38005 is a hardware platform designed to support advanced acoustic echo canceller (with noise reduction)
firmware applications available from Zarlink Semiconductor. These applications are resident in external memory
and are down-loaded by the ZL38005 resident boot code during initialization.
The firmware product and manual available at the release of this data sheet is the ZLS38501: Acoustic Echo
Canceller with Noise Reduction. If these applications do not meet your requirements, please contact your local
Zarlink Sales Office for the latest firmware releases.
The ZL38005 Advanced Acoustic Echo Canceller with Noise Reduction platform integrates Zarlink’s Voice
Processor (ZVP) DSP Core with a number of internal peripherals. These peripherals include the following:
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Two independent
∆Σ
CODECs
Two PCM ports - ST BUS, GCI, McBSP or SSI operation
An I
2
S interface port
A 2048 tap Filter Co-processor (LMS, FIR and FAP realizations)
Two Auxiliary Timers and a Watchdog Timer
11 GPIO pins
A UART interface
A Slave SPI port and a Master SPI port
A timing block that supports master and slave operation
An IEEE - 1149.1 compatible JTAG port
The DSP Core can process up to four 8-bit audio channels, two 16-bit audio channels or two 8-bit and one 16-bit
audio channel. These audio channels may originate and terminate with the
Σ∆
CODECs, or be communicated to
and from the DSP Core through the PCM ports or the I
2
S port.
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Zarlink Semiconductor Inc.
ZL38005
2.0
Core DSP Functional Block
Data Sheet
The ZL38005 DSP Core functional block, illustrated in Figure 1, is made up of a DSP Core, Interrupt Controller,
Data RAM, Instruction RAM, BOOT ROM Hardware Accelerators. This block controls the timing (APLL and Timing
Generator), peripheral interfaces through a peripheral address/data/control bus.
The ZL38005 implementation of DSP core and Filter Co-processor have been optimized to efficiently support voice
processing applications. These applications are described in detail in the Firmware Manuals associated with this
hardware platform.
2.1
DSP
The Core DSP is a 100 MIPS processor realized with two internal memory busses (Harvard architecture) to allow
multiple accesses during the same instruction cycle. In addition the DSP uses hardware accelerators and a filter co
processor that can be reused for different applications.
The Filter Co-Processor is used by the application firmware to realize the LMS filters up to a maximum of 2048
coefficients (taps).
3.0
Codec[1:0]
The ZL38005 has two 16-bit fully differential
∆Σ
DACs (DAC 0/1) that meets G.712 requirements at 8 kHz sampling
The ADC path consists of input signal pins C0/1_ADCi+ and C0/1_ADCi- (buffer output pins C0/1_BF0+ and
C0/1_BFo-), which feed selectable Microphone Amplifier or Line Amplifier options. The ADC sampling is 8KHz.
4.0
4.1
PCM Port
PCM Port
The PCM port support data communication between an external peripheral device and the ZL38005 DSP Core
using separate input (PCMi) and output (PCMo) serial streams with TDM (i.e., ST-BUS, GCI or McBSP) or SSI
interface timing. Access to the control and status registers associated with these ports is through the Slave SPI port
UART. These port signals are either in their input or high impedance states after a power-on reset and outputs
signals PCMo may be put in a high impedance state at any time during normal operation. Refer to the associated
Firmware Manual for PCM port control, status and mode selection.
Figure 2 illustrates the signals associated with the Master and Slave timing modes of operation for PCM Port. Insert
A: PCM port Master TDM (Mode 0), shows data clock (PCM_CLKo) and frame pulse (PCMFP) as outputs derived
from the ZL38005 internal PLL. PCM_CLKo clocks data into the ZL38005 on PCMCMi and out of the ZL38005 on
PCMo, and PCMFP delineates the 8 kHz frame boundaries for these signals. Insert B: PCM Master SSI (Mode3),
functions the same way as the TDM Master except that selected channels are defined by enable outputs P0ENA1
and P0ENA2.
With slave operation the source of timing is not the ZL38005, so PCM_CLKi is the input clock and PCMFP is the
8 kHz input frame pulse. This is illustrated by Figure 2 C: PCM Port Slave TDM (Modes 1 & 2) and D: PCM Port
Slave SSI (Modes 4, 5 & 6).
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Zarlink Semiconductor Inc.
ZL38005
ZL38005
ZL38005
Data Sheet
P_CLKo
P0FP
PCM_CLKi or
PCM_LBCi*
P0FP
PCMo
PCMi
PCMo
PCMi
A: Master TDM (Mode 0)
C: Slave TDM (Modes 1 & 2)
ZL38005
ZL38005
PCM_CLKi or
PCM_LBCi*
PCMENA1
PCMENA2
PCMo
PCMi
PCM_CLKo
PCMENA1
PCMENA2
PCMo
PCMi
B: Master SSI (Mode 3)
D: Slave SSI (Modes 4, 5 & 6)
* OSCi/OSCo must be used when the Low Bit Rate Clock (PCM_LBCi) is used
Figure 2 - PCM Port Signal Configurations for Master/Slave Operation
The ZL38005 will process audio channels of up to 16 bits in length. Audio channel sizes are designated as either 8-
bit (Short) or 16-bit (Long) on the PCM interfaces. With TDM operation each audio channel is mapped on to one or
more 8-bit time slots that are defined by the associated frame alignment signal. Each PCM port (0 & 1) supports
from 1 to 4 Short Channels; 1 or 2 Short Channels and 1 Long (16-bit) Channel; or 2 Long Channels. Audio
channels are defined as First and Second Long, and First, Second, Third and Fourth Short, see the Firmware
Manual for assignment details. These channels may be assigned to different time slots on the input and output
streams.
In SSI mode each PCM port supports 1 or 2 Short or Long channels, which are defined on PCMi0 by the position
and length of enable signals P0ENA1 and P0ENA2. Audio channels are defined as First and Second Long, and
First and Third Short, see the Firmware Manual for assignment details. Channel positions and length are common
to input and output signals.
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Zarlink Semiconductor Inc.
ZL38005
4.2
SSI Operation
Data Sheet
Figures 3 illustrates the SSI functional timing used when the two enable strobes (audio channels) are separated by
a non-zero number of bit clock cycles. Here the enable signal polarities are active low, either bit clock polarity may
be selected. In this format frames are delineated by the active edge of PCMENA1 minus 1/2 bit clock cycle. The
frame repetition rate is 8 kHz. See Firmware Manual to program the positions of the Audio Channels within the
8 kHz frame.
PCMENA1
PCMfpP = PSSISSP = 0
PCMfpS[1:0] = 00
PCMENA2
Master/Slave Clock
PCLKP = 1
Master/Slave Clock
PCLKP = 0
Channel 0
Channel 1
7 6 5 4 3 2 1 0
Channel 1
7 6 5 4 3 2 1 0
PCMi
7 6 5 4 3 2 1 0
Channel 0
PCMo
7 6 5 4 3 2 1 0
Master Clock - output clocks PCM_CLKo
Slave Clock - input clocks PCM_CLKi or PCM_LBCi
Note: PCMi/o are shown as 8-bit audio channels; however, the timing options illustrated here are applicable to 16-
bit audio channels as well
Figure 3 - SSI Mode: Separated Channels Functional Timing
4.3
I
2
S Port Description
The I
2
S (Inter-IC Sound) port and PCM Port One share the same physical pins of the ZL38005. Selection of either
I
2
S port operation or PCM Port One operation is done through the Port One PCM/I
2
S Select Register. See
Firmware Manual.
The I
2
S port can be used to connect external Analog-to-Digital Converters or CODECs to the internal DSP. This
port can operate in master mode, where the ZL38005 is the source of the port clocks, or slave mode, where the bit
and sampling clocks (I
2
S_SCK and I
2
S_ LRCK) are inputs to the ZL38005. The master clock (I
2
S_MCLK) is always
an output. In I
2
S port master mode the clock signal at output pin I
2
S_LRCK is the sampling frequency (f
S
), the clock
signal at output I
2
S_SCK is 32 x f
S
, and the clock signal at output I
2
S_MCLK is 256 x f
S
. In I
2
S port slave mode the
relationship between the clock signal at input pin I
2
S_LRCK and the clock signal at input I
2
S_SCK must be 32 x f
S
.
In slave mode the 256 x f
S
relationship between f
S
and the I
2
S_MCLK is not mandatory, and the I
2
S_MCLK output
pin will be in a high impedance state. See Firmware Manual for I
2
S programming options.
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