EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

DM74AS162N/A+

Description
IC,COUNTER,UP,DECADE,AS-TTL,DIP,16PIN,PLASTIC
Categorylogic   
File Size426KB,7 Pages
ManufacturerNational Semiconductor(TI )
Websitehttp://www.ti.com
Stay tuned Parametric

DM74AS162N/A+ Overview

IC,COUNTER,UP,DECADE,AS-TTL,DIP,16PIN,PLASTIC

DM74AS162N/A+ Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerNational Semiconductor(TI )
package instructionDIP, DIP16,.3
Reach Compliance Codeunknown
Is SamacsysN
Counting directionUP
JESD-30 codeR-PDIP-T16
JESD-609 codee0
Load/preset inputYES
Logic integrated circuit typeDECADE COUNTER
Operating modeSYNCHRONOUS
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Base Number Matches1
PCB Engineering Issues
There are a few small arrows under the red pen, it seems that there was no such thing before; please explain it to me...
NJMKL PCB Design
Analysis of white light emitting diode backlight source and its driving circuit design
In recent years, the industry has begun to use LEDs to replace CCFL and EL as LCD backlights (short for background lighting ). Compared with CCFL and EL, LEDs have the following advantages:   1) It ca...
探路者 LED Zone
How to find the reciprocal in FPGA
What I need to do first is to calculate the reciprocal of a fixed-point real number. I use 16 bits to represent real numbers in the range of 1.0 to 15.0, 4 bits to represent integers, and 11 bits to r...
wang182004 FPGA/CPLD
IAR Compile Error
Error[Pe144]: a value of type "char const [17]" cannot be used to initialize an entity of type "unsigned char const [16]" const u8 testinf2[16]={" Please wait .. "}; There are 16 numbers in an array. ...
eeacc stm32/stm8
【Altera SoC Experience Tour】Video Server Based on SocKit
This experiment is based on the official demonstration program. We will first introduce the experimental phenomena and then study the specific technical details. The basic principle of this experiment...
rowen800 FPGA/CPLD
Quartus II 13.0 sp1 cannot be activated, urgent help
It should support genuine products, but I am short of money. I can only use cracking:pleased: I installed Quartus II 13sp1 on Windows Server 2008 64-bit system. The path does not have Chinese characte...
wsmysyn FPGA/CPLD

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2726  2442  31  1317  2638  55  50  1  27  54 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号