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DM54LS138J

Description
Decoder/Driver, LS Series, Inverted Output, TTL, CDIP16, CERAMIC, DIP-16
Categorylogic   
File Size376KB,8 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
Download Datasheet Parametric View All

DM54LS138J Overview

Decoder/Driver, LS Series, Inverted Output, TTL, CDIP16, CERAMIC, DIP-16

DM54LS138J Parametric

Parameter NameAttribute value
MakerRochester Electronics
package instructionDIP,
Reach Compliance Codeunknown
ECCN codeEAR99
Is SamacsysN
seriesLS
Input adjustmentSTANDARD
JESD-30 codeR-GDIP-T16
Logic integrated circuit typeOTHER DECODER/DRIVER
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityINVERTED
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
propagation delay (tpd)40 ns
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm
Base Number Matches1
54LS138 DM54LS138 DM74LS138
54LS139 DM54LS139 DM74LS139 Decoders Demultiplexers
June 1989
54LS138 DM54LS138 DM74LS138
54LS139 DM54LS139 DM74LS139
Decoders Demultiplexers
General Description
These Schottky-clamped circuits are designed to be used in
high-performance memory-decoding or data-routing appli-
cations requiring very short propagation delay times In
high-performance memory systems these decoders can be
used to minimize the effects of system decoding When
used with high-speed memories the delay times of these
decoders are usually less than the typical access time of the
memory This means that the effective system delay intro-
duced by the decoder is negligible
The LS138 decodes one-of-eight lines based upon the con-
ditions at the three binary select inputs and the three enable
inputs Two active-low and one active-high enable inputs
reduce the need for external gates or inverters when ex-
panding A 24-line decoder can be implemented with no ex-
ternal inverters and a 32-line decoder requires only one
inverter An enable input can be used as a data input for
demultiplexing applications
The LS139 comprises two separate two-line-to-four-line de-
coders in a single package The active-low enable input can
be used as a data line in demultiplexing applications
All of these decoders demultiplexers feature fully buffered
inputs presenting only one normalized load to its driving
circuit All inputs are clamped with high-performance
Schottky diodes to suppress line-ringing and simplify system
design
Features
Y
Y
Y
Y
Y
Y
Y
Connection Diagrams
O
TL F 6391 – 1
TL F 6391 – 2
Order Number 54LS138DMQB 54LS138FMQB
54LS138LMQB DM54LS138J DM54LS138W
DM74LS138M or DM74LS138N
See NS Package Number E20A J16A
M16A N16E or W16A
C
1995 National Semiconductor Corporation
TL F 6391
bs
ol
Dual-in-Line Package
Designed specifically for high speed
Memory decoders
Data transmission systems
LS138 3-to-8-line decoders incorporates 3 enable in-
puts to simplify cascading and or data reception
LS139 contains two fully independent 2-to-4-line decod-
ers demultiplexers
Schottky clamped for high performance
Typical propagation delay (3 levels of logic)
LS138 21 ns
LS139 21 ns
Typical power dissipation
LS138 32 mW
LS139 34 mW
Alternate
Military Aerospace
devices
(54LS138
54LS139) are available Contact a National Semicon-
ductor Sales Office Distributor for specifications
et
Dual-in-Line Package
Order Number 54LS139DMQB 54LS139FMQB
54LS139LMQB DM54LS139J DM54LS139W
DM74LS139M or DM74LS139N
See NS Package Number E20A J16A
M16A N16E or W16A
RRD-B30M105 Printed in U S A
e

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