5962R9582001VXC datasheet, PDF

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5962R9582001VXC: Description15 MHz, PROC SPECIFIC CLOCK GENERATOR, CDFP24; Categorysemiconductor The embedded processor and controller; File Size153KB，16 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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15 MHz, PROC SPECIFIC CLOCK GENERATOR, CDFP24

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HS-82C85RH

Data Sheet

August 2000

File Number

3044.2

Radiation Hardened CMOS Static Clock

Controller/Generator

The Intersil HS-82C85RH is a high performance, radiation

hardened CMOS Clock Controller/Generator designed to

support systems utilizing radiation hardened static CMOS

microprocessors such as the HS-80C86RH. The

HS-82C85RH contains a crystal controlled oscillator, reset

pulse conditioning, halt/restart logic, and divide-by-256

circuitry. These features provide the means to stop the

system clock, stop the clock oscillator, or run the system at a

low frequency (CLK/256), enhancing control of static system

power dissipation and allowing system shut-down during

periods of external stress.

Static CMOS circuit design insures low operating power and

permits operation with an external frequency source from

DC to 15MHz. Crystal controlled operation to 15MHz is

guaranteed with the use of a parallel, fundamental mode

crystal and two small load capacitors. Outputs are

guaranteed compatible with both CMOS and TTL

speciﬁcations. The Intersil hardened ﬁeld CMOS process

results in performance equal to or greater than existing

radiation resistant products at a fraction of the power.

Speciﬁcations for Rad Hard QML devices are controlled

by the Defense Supply Center in Columbus (DSCC). The

SMD numbers listed here must be used when ordering.

Detailed Electrical Speciﬁcations for these devices are

contained in SMD 5962-95820. A “hot-link” is provided

on our homepage for downloading.

www.intersil.com/spacedefense/space.asp

Features

• Electrically Screened to SMD # 5962-95820

• QML Qualiﬁed per MIL-PRF-38535 Requirements

• Radiation Hardened

- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)

- Transient Upset . . . . . . . . . . . . . . . . . . . . >10

rad(Si)/s

- Latch Up Free EPI-CMOS

• Very Low Power Consumption

• Pin Compatible with NMOS 8285 and Intersil 82C85

• Generates System Clocks for Microprocessors and

Peripherals

• Complete Control Over System Clock Operation for Very

Low System Power

- Stop-Oscillator

- Stop-Clock

- Low Frequency (Slo) Mode

- Full Speed Operation

• DC to 15MHz Operation (DC to 5MHz System Clock)

• Generates Both 50% and 33% Duty Cycle Clocks

(Synchronized)

• Uses Either Parallel Mode Crystal Circuit or External

Frequency Source

• Hardened Field, Self-Aligned, Junction Isolated CMOS

Process

• Single 5V Supply

• Military Temperature Range . . . . . . . . . . . -55

C to 125

Ordering Information

ORDERING NUMBER

5962R9582001VJC

5962R9582001VXC

HS9-82C85RH/Proto

INTERNAL

MKT. NUMBER

HS1-82C85RH-Q

HS9-82C85RH-Q

HS9-82C85RH/Proto

TEMP. RANGE

(

-55 to 125

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil and Design is a trademark of Intersil Corporation.

HS-82C85RH

Pin Descriptions

SLO/FST

NUMBER

(Continued)

TYPE

DESCRIPTION

SLO/FST is a level-triggered input. When HIGH, the CLK and CLK50 outputs run at the maximum

frequency (crystal or EFI frequency divided by 3). When LOW, CLK and CLK50 frequencies are equal to

the crystal or EFI frequency divided by 768. SLO/FST mode changes are internally synchronized to

eliminate glitches on the CLK and CLK50. START and STOP control of the oscillator or EFI is available

in either the SLOW or FAST frequency modes.

The SLO/FST input must be held LOW for at least 195 OSC/EFI clock cycles before it will be recognized.

This eliminates unwanted frequency changes which could be caused by glitches or noise transients. The

SLO/FST input must be held HIGH for at least 6 OSC/EFI clock pulses to guarantee a transition to FAST

mode operation.

PROCESSOR CLOCK: CLK is the clock output used by the HS-80C86RH processor and other

peripheral devices. When SLO/FST is high, CLK has an output frequency which is equal to the crystal or

EFI input frequency divided by three. When SLO/FST is low, CLK has an output frequency which is equal

to the crystal or EFI input frequency divide by 768. CLK has a 33% duty cycle.

50% DUTY CYCLE CLOCK: CLK50 is an auxiliary clock with a 50% duty cycle and is synchronized to

the falling edge of CLK. When SLO/FST is high, CLK50 has an output frequency which is equal to the

crystal or EFI input frequency divided by 3. When SLO/FST is low, CLK50 has an output frequency equal

to the crystal or EFI input frequency divided by 768.

PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is equal to the crystal

or EFI input frequency divided by six and has a 50% duty cycle. PCLK frequency is unaffected by the

state of the SLO/FST input.

OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal to

that of the crystal oscillator circuit. OSC is unaffected by the state of the SLO/FST input.

When the HS-82C85RH is in the crystal mode (F/C LOW) and a STOP command is issued, the OSC

output will stop in the HIGH state. When the HS-82C85RH is in the EFI mode (F/C HIGH), the oscillator

(if operational) will continue to run when a STOP command is issued and OSC remains active.

RESET IN: RES is an active LOW signal which is used to generate RESET. The HS-82C85RH provides

a Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper

duration. RES starts crystal oscillator operation.

RESET: RESET is an active HIGH signal which is used to reset the HS-80C86RH processor. Its timing

characteristics are determined by RES. RESET is guaranteed to be HIGH for a minimum of 16 CLK

pulses after the rising edge of RES.

CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple HS-82C85RHs to

be synchronized to provide multiple in-phase clock signals. When CSYNC is HIGH, the internal counters

are reset and force CLK, CLK50 and PCLK into a HIGH state. When CSYNC is LOW, the internal

counters are allowed to count and the CLK, CLK50 and PCLK outputs are active. CSYNC must be

externally synchronized to EFI.

ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready

Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are

useful in system configurations which permit the processor to access two Multi-Master System Buses.

BUS READY: (Transfer Complete). RDY is an active HIGH signal which is an indication from a device

located on the system data bus that data has been received, or is available. RDY1 is qualified by AEN1

while RDY2 is qualified by AEN2.

READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization mode of

the READY logic. When ASYNC is LOW, two stages of READY synchronization are provided. When

ASYNC is left open or HIGH a single stage of READY synchronization is provided.

READY: READY is an active HIGH signal which is used to inform the HS-80C86RH that it may conclude

a pending data transfer.

Ground

+5V power supply

CLK

CLK50

PCLK

OSC

RES

RESET

CSYNC

AEN1

AEN2

RDY1

RDY2

ASYNC

READY

GND

5962R9582001VXC Related Products

	5962R9582001VXC	5962R9582001VJC	HS9-82C85RH/Proto	HS-82C85RH	HS1-82C85RH	HS1-82C85RH-Q	HS9-82C85RH	HS9-82C85RH-Q
Description	15 MHz, PROC SPECIFIC CLOCK GENERATOR, CDFP24	15 MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP24	5 MHz, PROC SPECIFIC CLOCK GENERATOR, CDFP24	15 MHz, PROC SPECIFIC CLOCK GENERATOR, CDFP24	15 MHz, PROC SPECIFIC CLOCK GENERATOR, CDFP24	15 MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP24	15 MHz, PROC SPECIFIC CLOCK GENERATOR, CDFP24	15 MHz, PROC SPECIFIC CLOCK GENERATOR, CDFP24

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