IMAGE SENSOR
CCD area image sensor
S8665-0909
Four-stage thermoelectric cooled, back-thinned FFT-CCD
S8665-0909 is an FFT-CCD area image sensor featuring low noise and low dark current (MPP mode operation). The output charge can be
integrated for long periods of time even at low light levels, allowing a wide dynamic range.
S8665-0909 uses a four-stage thermoelectric cooler that cools the CCD down to -50 ˚C when operated at room temperatures, achieving even
lower noise and dark current.
Features
Applications
l
Four-stage TE-cooled
l
Number of active pixels: 512 (H)
×
512 (V)
l
Pixel size: 24
×
24 µm
l
100 % fill factor
l
Wide dynamic range
l
Low dark current
l
Low readout noise
l
MPP operation
l
Astronomy
l
Scientific measuring instrument
l
UV imaging
l
For low-light-level detection requiring
I
Selection guide
Type No.
S8665-0909
Cooling
Four-stage
TE-cooled
Number of total pixels
532
´
520
Number of active
pixels
512
´
512
Active area
[mm (H) × mm (V)]
12.288
´
12.288
I
Specifications
Parameter
CCD structure
Fill factor
Cooling
Number of pixels
Number of active pixels
Pixel size
Active area
Vertical clock phase
Horizontal clock phase
Output circuit
Package
Window
Specification
Full frame transfer
100 %
Four-stage TE-cooled
532 (H) × 520 (V)
512 (H) × 512 (V)
24 (H) × 24 (V) µm
12.288 (H) × 12.288 (V) mm
2 phase
2 phase
One-stage MOSFET source follower
28 pin metal package
AR coated sapphire
1
CCD area image sensor
I
Absolute maximum ratings (Ta=25 °C)
Parameter
Operating temperature
Storage temperature
OD voltage
RD voltage
ISV voltage
ISH voltage
IGV voltage
IGH voltage
SG voltage
OG voltage
RG voltage
TG voltage
Vertical clock voltage
Horizontal clock voltage
S8665-0909
Max.
+30
+70
+25
+18
+18
+18
+15
+15
+15
+15
+15
+15
+15
+15
Unit
°C
°C
V
V
V
V
V
V
V
V
V
V
V
V
Symbol
Topr
Tstg
V
OD
V
RD
V
ISV
V
ISH
V
IG1V
, V
IG2V
V
IG1H
, V
IG2H
V
SG
V
OG
V
RG
V
TG
V
P1V
, V
P2V
V
P1H
, V
P2H
Min.
-50
-50
-0.5
-0.5
-0.5
-0.5
-10
-10
-10
-10
-10
-10
-10
-10
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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Operating conditions (MPP mode, Ta=25 °C)
Parameter
Output transistor drain voltage
Reset drain voltage
Output gate voltage
Substrate voltage
Test point (vertical input source)
Test point (horizontal input source)
Test point (vertical input gate)
Test point (horizontal input gate)
High
Vertical shift register
clock voltage
Low
High
Horizontal shift register
clock voltage
Low
High
Summing gate voltage
Low
High
Reset gate voltage
Low
High
Transfer gate voltage
Low
Symbol
V
OD
V
RD
V
OG
V
SS
V
ISV
V
ISH
V
IG1V
, V
IG2V
V
IG1H
, V
IG2H
V
P1VH
, V
P2VH
V
P1VL
, V
P2VL
V
P1HH
, V
P2HH
V
P1HL
, V
P2HL
V
SGH
V
SGL
V
RGH
V
RGL
V
TGH
V
TGL
Min.
18
11.5
1
-
-
-
-8
-8
4
-9
4
-9
4
-9
4
-9
4
-9
Typ.
20
12
3
0
V
RD
V
RD
0
0
6
-8
6
-8
6
-8
6
-8
6
-8
Max.
22
12.5
5
-
-
-
-
-
8
-7
8
-7
8
-7
8
-7
8
-7
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
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Electrical characteristics (Ta=25 °C)
Parameter
Symbol
Min.
Typ.
Signal output frequency
fc
-
-
Vertical shift register capacitance
C
P1V
, C
P2V
-
6,400
Horizontal shift register capacitance
C
P1H
, C
P2H
-
120
Summing gate capacitance
C
SG
-
7
Reset gate capacitance
C
RG
-
7
Transfer gate capacitance
C
TG
-
150
1
Charge transfer efficiency *
CTE
0.99995
0.99999
2
DC output level *
Vout
12
15
2
Output impedance *
Zo
-
3
Power consumption *
2
*
3
P
-
15
*1: Charge transfer efficiency per pixel, measured at half of the full well capacity.
*2: The values depend on the load resistance. (Typical, V
OD
=20 V, Load resistance=22 kW)
*3: Power consumption of the on-chip amplifier.
Max.
1
-
-
-
-
-
-
18
-
-
Unit
MHz
pF
pF
pF
pF
pF
-
V
kW
mW
2
CCD area image sensor
I
Electrical and optical characteristics (Ta=25 °C, unless otherwise noted)
Parameter
Symbol
Remark
Min.
Saturation output voltage
Vsat
-
-
Vertical
150
*
4
Full well capacity
Fw
Horizontal
300
*
5
CCD node sensitivity
Sv
1.8
+25 °C
-
Dark current
6
*
0 °C
DS
-
(MPP mode)
-30 °C
-
7
*
Readout noise
Nr
-
Line binning
-
*
8
Dynamic range
DR
Area scanning
-
Spectral response range
-
-
l
9
*
Photo response non-uniformity
PRNU
-
10
*
Point defect
-
11
*
Blemish
Cluster defect
-
-
*
12
Column defect
-
*4: Large horizontal full well capacity for line binning operation.
*5: V
OD
=20 V, load resistance=22 kW.
*6: Dark current nearly doubles for every 5 to 7 °C increase in temperature.
*7: -40 °C, operating frequency is 80 kHz.
*8: Dynamic range DR=Full well capacity/Readout noise
*9: Measured at half of the full well capacity output.
Photo response non-uniformity (PRNU) [%] =
Typ.
Fw × Sv
300
600
2.2
4,000
200
3
8
75,000
37,500
200 to 1100
-
-
-
-
S8665-0909
Max.
-
-
-
-
12,000
600
9
12
-
-
-
±10
10
3
0
Unit
V
ke
-
µV/e
-
e
-
/pixel/s
e
-
rms
-
nm
%
-
Fixed pattern noise (peak to peak)
× 100
Signal
*10: White spots > 3 % of full well at 0 °C after Ts=1 s, Black spots > 50 % reduction in response relative to adjacent pixels.
*11: Continuous 2 to 9 point defects.
*12: Continuous
³
10 point defects.
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Spectral response (without window) *
13
100
90
(Typ. Ta=25 ˚C)
BACK-THINNED
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Dimensional outline (unit: mm)
PIN No. 1
1st PIN
INDEX MARK
1.0
20.0
12.288
4.0
7.0
QUANTUM EFFICIENCY (%)
80
70
60
12.288
2
3
27
26
50
40
30
20
FRONT-ILLUMINATED
10
0
200
400
600
800
1000
1200
FRONT-ILLUMINATED
(UV COAT)
0.46
PINCHED
OFF TUBE
5.0
0.25
28
14
15
35.0
WAVELENGTH (nm)
KMPDB0058EA
47.0
*13: Spectral response with sapphire window is
decreased by the transmittance
SAPPHIRE
WINDOW
18.5 ± 0.5
50.8
KMPDA0142EB
6.5 ± 0.5
2.54
12
13
17
16
27.94
36.0
44.0
50.0
3
CCD area image sensor
I
Dark current vs. temperature
10000
(Typ.)
S8665-0909
DARK CURRENT (e
-
/pixel/s)
1000
100
10
1
0.1
-50
-40
-30
-20
-10
0
10
20
30
TEMPERATURE (˚C)
KMPDB0037EB
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Device structure
THINNING
6
7
5
3
24
23
25
4 BEVEL
THINNING
V
8
9
10
5
4
3
2
12345
H
22
21
11
12
13
18
19
20
V=512
H=512
4 BLANK
512 SIGNAL OUT
4 BLANK
8 BEVEL
4 BEVEL
KMPDC0075EB
4
4 BEVEL
512 SIGNAL OUT
CCD area image sensor
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PIN connections
Pin No.
Symbol
Description
1
P-
TE-cooler-
2
NC
3
SS
Substrate (GND)
4
NC
5
ISV
Test point (vertical input source)
6
IG2V
Test point (vertical input gate-2)
7
IG1V
Test point (vertical input gate-1)
8
RG
Reset gate
9
RD
Reset drain
10
OS
Output transistor source
11
OD
Output transistor drain
12
OG
Output gate
13
SG
Summing gate
14
P+
TE-cooler+
15
TSH1
Temperature sensor (hot side)
16
TSC1
Temperature sensor (cool side)
17
TSC2
Temperature sensor (cool side)
18
P2H
CCD horizontal register clock-2
19
P1H
CCD horizontal register clock-1
20
IG2H
Test point (horizontal input gate-2)
21
IG1H
Test point (horizontal input gate-1)
22
ISH
Test point (horizontal input source)
23
P2V
CCD vertical register clock-2
24
P1V
CCD vertical register clock-1
25
TG
Transfer gate
26
NC
27
NC
28
TSH2
Temperature sensor (hot side)
*14: TG is an isolation gate between vertical register and horizontal resister.
In standard operation, the same pulse of P2V should be applied to the TG.
S8665-0909
Remark
Shorted to RD
Shorted to 0 V
Shorted to 0 V
Same timing as P2H
Shorted to 0 V
Shorted to 0 V
Shorted to RD
Same timing as P2V *
14
5
MCU
京公网安备 11010802033920号
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