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IDT709089S9PF9

Description
Dual-Port SRAM, 64KX8, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
Categorystorage   
File Size199KB,18 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT709089S9PF9 Overview

Dual-Port SRAM, 64KX8, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT709089S9PF9 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instruction14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Is SamacsysN
Maximum access time20 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 codeS-PQFP-G100
JESD-609 codee0
length14 mm
memory density524288 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count65536 words
character code64000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX8
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width14 mm
Base Number Matches1
HIGH-SPEED 64/32K x 8
SYNCHRONOUS
DUAL-PORT STATIC RAM
Features:
IDT709089/79S/L
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6/7/9/12/15ns (max.)
– Industrial: 12ns (max.)
Low-power operation
– IDT709089/79S
Active: 950mW (typ.)
Standby: 5mW (typ.)
– IDT709089/79L
Active: 950mW (typ.)
Standby: 1mW (typ.)
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE
pin
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data,
and address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in the Pipelined
output mode
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in 100-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/W
L
OE
L
CE
0L
CE
1L
R/W
R
OE
R
CE
0R
CE
1R
1
0
0/1
1
0
0/1
FT/PIPE
L
0/1
1
0
0
1
0/1
FT/PIPE
R
I/O
0L
- I/O
7L
I/O
Control
I/O
Control
I/O
0R
- I/O
7R
A
15L
(1)
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
15R
(1)
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
3242 drw 01
.
NOTE:
1. A
15
X
is a NC for IDT709079.
JUNE 2004
1
©2004 Integrated Device Technology, Inc.
DSC-3242/12
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