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8530DYI-01LF

Description
PTQFP-48, Tray
Categorylogic   
File Size558KB,19 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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8530DYI-01LF Overview

PTQFP-48, Tray

8530DYI-01LF Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codePTQFP
package instructionHTFQFP, QFP48,.35SQ,20
Contacts48
Manufacturer packaging codeDXG48
Reach Compliance Codecompliant
ECCN codeEAR99
Is SamacsysN
series8530
Input adjustmentDIFFERENTIAL
JESD-30 codeS-PQFP-G48
JESD-609 codee3
length7 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level3
Number of functions1
Number of inverted outputs
Number of terminals48
Actual output times16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeHTFQFP
Encapsulate equivalent codeQFP48,.35SQ,20
Package shapeSQUARE
Package formFLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup2 ns
propagation delay (tpd)2 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.075 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width7 mm
Base Number Matches1
Low Skew, 1-to-16 Differential-to-3.3V
LVPECL Fanout Buffer
8530I-01
Datasheet
General Description
The 8530I-01is a low skew, 1-to-16 Differential- to-3.3V LVPECL
Fanout Buffer. The CLK, nCLK pair can accept most standard
differential input levels. The high gain differential amplifier accepts
peak-to-peak input voltages as small as 150mV as long as the
common mode voltage is within the specified minimum and
maximum range.
Guaranteed output and part-to-part skew characteristics make the
8530I-01 ideal for those clock distribution applications demanding
well defined performance and repeatability.
Features
Sixteen differential 3.3V LVPECL output pairs
CLK, nCLK input pair
CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V LVPECL levels
with a resistor bias on nCLK input
Output skew: 75ps (maximum)
Additive phase jitter, RMS @ 106.25MHz: 0.162ps (typical)
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK0
Pulldown
nCLK0
Pullup
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
Pin Assignment
Q12
nQ13
Q13
V
EE
nQ14
Q14
V
CCO
nQ12
nCLK
nQ15
Q15
V
CCO
V
CCO
Q11
nQ11
Q10
nQ10
V
EE
Q9
nQ9
Q8
nQ8
V
CCO
V
CC
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
5
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
V
CC
V
CCO
Q7
nQ7
Q6
nQ6
V
EE
Q5
nQ5
Q4
nQ4
V
CCO
CLK
V
CCO
nQ0
Q0
nQ1
Q1
V
EE
nQ2
Q2
nQ3
Q3
V
CCO
8530I-01
48-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm package body
Y Package
Top View
©2015 Integrated Device Technology, Inc.
1
Revision B, December 1, 2015
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