CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
V
S+
I
S+
Supply Voltage
V
SD
= 3V, V
S
+ = 15V, A
VDD
= 15V, R
SET
= 24.9k, and T
A
= +25°C unless otherwise specified.
CONDITION
MIN
4.5
EL9200
EL9201
EL9202
3.8
7.6
10.5
3
2.6
TYP
MAX
16.5
4.8
9.6
16
3.6
3.6
50
25
23
3
25
0.7*V
SD
0.2*V
SD
20
20
200
200
10
CTL = GND
CTL = V
SD
10
10
10
2.6V < V
SD
< 3.6V
2.6V < V
SD
< 3.6V
(Note 1)
2.6V < V
SD
< 3.6V (Note 2)
> 4.9V
1.6
1
4.9
200
100
(Note 5)
1000
15.75
0.4
0.8*V
SD
0.3*V
SD
UNIT
V
mA
mA
mA
V
V
µA
µA
mA
mA
µA
V
V
µs
µs
µs
µs
µs
µA
µA
pF
V
V
ms
V
µs
ms
cycles
DESCRIPTION
Quiescent Current
V
SD
Logic Supply Voltage
For programming
For operation
I
SD
Quiescent Logic Current
CE = 3.6V
CE = GND
Program (charge pump current) (Note 1)
Read (Note 1)
I
ADD
CTL
IH
CTL
IL
CTL
IHRPW
CTL
ILRPW
CTL
IHMPW
CTL
ILMPW
CTL
MTC
ICTL
Supply Current
CTL High Voltage
CTL Low Voltage
CTL High Rejected Pulse Width
CTL Low Rejected Pulse Width
CTL High Minimum Pulse Width
CTL Low Minimum Pulse Width
CTL Minimum Time Between Counts
CTL Input Current
(Note 2)
2.6V < V
SD
< 3.6V
2.6V < V
SD
< 3.6V
CTL
CAP
CE
IL
CE
IH
CE
ST
CTL
PROM
CTL
PT
P
T
EE
WC
CTL Input Capacitance
CE Input Low Voltage
CE Input High Voltage
CE Minimum Start-Up Time
CTL EEPROM Program Voltage
CTL EEPROM Programming Signal
Time
Programming Time
EE Write Cycles
FN7438 Rev 1.00
October 30, 2008
Page 3 of 15
EL9200, EL9201, EL9202
Electrical Specifications
PARAMETER
SET
DN
SET
ZSE
SET
FSE
I
SET
SET
ER
V
SD
= 3V, V
S
+ = 15V, A
VDD
= 15V, R
SET
= 24.9k, and T
A
= +25°C unless otherwise specified.
(Continued)
CONDITION
Monotonic over-temperature
(Note 3)
(Note 3)
Through R
SET
(Note 1)
To GND, A
VDD
= 20V (Note 1)
To GND, A
VDD
= 4.5V (Note 1)
A
VDD
to SET
OUT
ST
V
OUT
OUT
VD
A
VDD
to SET Voltage Attenuation
OUT Settling Time
OUT Voltage Range
OUT Voltage Drift
To ±0.5 LSB error band (Note 1)
(Note 1)
(Note 1)
V
SET
+ 0.5V
10
2.25
1:20
20
13
10
MIN
TYP
±1
±2
±8
120
200
45
MAX
UNIT
LSB
LSB
LSB
µA
k
k
V/V
µs
V
mV
DESCRIPTION
SET Differential Nonlinearity
SET Zero-Scale Error
SET Full-Scale Error
SET Current
SET External Resistance
AMPLIFIER CHARACTERISTICS
INPUT CHARACTERISTICS
V
OS
TCV
OS
I
B
R
IN
C
IN
CMRR
A
VOL
Input Offset Voltage
Average Offset Voltage Drift (Note 1)
Input Bias Current
Input Impedance
Input Capacitance
Common-Mode Rejection Ratio
Open-Loop Gain
For V
IN
from -5.5V to +5.5V
-4.5V
V
OUT
+4.5V
50
60
V
CM
= 0V
V
CM
= 0V
3
7
2
1
2
70
70
60
15
mV
µV/°C
nA
G
pF
dB
dB
OUTPUT CHARACTERISTICS
V
OL
V
OH
I
SC
I
OUT
Output Swing Low
Output Swing High
Short-Circuit Current
Output Current
R
L
= 1.5k to 0
14.85
±150
0.09
14.9
±180
±65
0.15
V
V
mA
mA
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
V
S+
is moved from 4.5V to 15.5V
-4.0V
V
OUT
4.0V,
20% to 80%
(A
V
= +1), V
OUT
= 2V step
55
80
dB
DYNAMIC PERFORMANCE
SR
t
S
BW
GBWP
PM
CS
d
G
d
P
NOTES:
1. Simulated and determined via design and not directly tested
2. Tested at A
VDD
= 20V
3. Wafer sort only
4. NTSC signal generator used
5. Limits established by characterization and are not production tested.
Slew Rate (Note 4)
Settling to +0.1% (A
V
= +1)
-3dB Bandwidth
Gain-Bandwidth Product
Phase Margin
Channel Separation
Differential Gain (Note 5)
Differential Phase (Note 5)
f = 5MHz (EL9201 and EL9202 only)
R
F
= R
G
= 1kand V
OUT
= 1.4V
R
F
= R
G
= 1kand V
OUT
= 1.4V
60
80
80
44
32
50
110
0.17
0.24
V/µs
ns
MHz
MHz
°
dB
%
°
FN7438 Rev 1.00
October 30, 2008
Page 4 of 15
EL9200, EL9201, EL9202
Pin Descriptions
PIN
VINx-
IN/OUT
Input
DESCRIPTION
Amplifier x inverting input, where:
x = A for EL9200
x = A, B for EL9201
x = A, B, C, D for EL9202
EQUIVALENT CIRCUIT
V
S+
GND
CIRCUIT 1
VINx+
Input
Amplifier x non-inverting input, where:
x = A for EL9200
x = A, B for EL9201
x = A, B, C, D for EL9202
Op amp supply; bypass to GND with 0.1µF capacitor
Amplifier X output, where:
x = A for EL9200
x = A, B for EL9201
x = A, B, C, D for EL9202
Reference Circuit 1
VS+
VOUTX
Supply
Output
V
S+
GND
CIRCUIT 2
GND
NC
GND
IOUT
-
Supply
Output
No connect; not internally connected
Ground connection
Adjustable sink current output pin; the current sinks into the
OUT pin is equal to the DAC setting times the maximum
adjustable sink current divided by 128; see SET pin function
description for the maxim adjustable sink current setting
Maximum sink current adjustment point; connect a resistor
from SET to GND to set the maximum adjustable sink
current of the OUT pin; the maximum adjustable sink
current is equal to (A
VDD
/20) divided by R
SET
Counter enable pin; connect CE to V
DD
to enable counting
of the internal counter; connect CE to GND to inhibit
counting
Internal counter up/down control and internal EEPROM
programming control input; if CE is high, a mid-to-low
transition increments the 7-bit counter, raising the DAC
setting, increasing the OUT sink current, and lowering the
divider voltage at OUT; a mid-to-high transition decrements
the 7-bit counter, lowering the DAC setting, decreasing the
OUT sink current, and increasing the divider voltage at
OUT; applying 4.9V and above with appropriately arranged
timing will overwrite EEPROM with the contents in the 7-bit
counter; see EEPROM Programming section for details
Analog voltage supply; bypass to GND with 0.1µF
capacitor
System power supply input; bypass to GND with 0.1µF
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