531EC327M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > oscillator> 531EC327M000DG

531EC327M000DG: DescriptionLVPECL Output Clock Oscillator, 327MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; Categoryoscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531EC327M000DG Overview

LVPECL Output Clock Oscillator, 327MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531EC327M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Is Samacsys	N
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	327 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Industrial four-way programmable controller circuit

C523 double column vertical lathe main circuit

555 electric fan integrated controller circuit

4096-bit CCDP driver circuit

2~35V, 10A adjustable regulated power supply composed of μA723

Internal structure diagram of IR2130

3*1W isolated drive solution; difficult to pass safety regulations: The FSEZ1317 solution currently being debugged: Input 85-265 Output 10V 350MA Passed EMI However, due to the limitation of the 30mm diameter round PCB board, the primary and secondary sides of the EE1...; czf0408 LED Zone

How to extract files after manual wiring in FPGA_EDITOR: How to extract files after manual wiring in FPGA_EDITOR I used the VERTIEX4 chip and manually laid out and routed it using FPGA-EDITOR to generate ncd and pcf files. But now I have a problem: I don't ...; eeleader FPGA/CPLD

How to make the semi-transparent menu above the video player in WinCE?: First of all, I think it is not realistic to use GDI, because the video is playing, and the things below are variable, and it is difficult to make semi-transparent. Secondly, use OpenGl ES? The entire...; cdj86cdj86 Embedded System

See you in April丨The 2021 Munich Shanghai Electronics Show is about to start, and pre-registration is in full swing!: Since entering China in 2002, the Munich Shanghai Electronics Fair (electronica China) has been diligently cultivating the Chinese electronics industry for nearly 20 years. With its strong brand influ...; eric_wang Talking

New moderator report, greetings to everyone: Hello everyone, I am the new moderator. I would like to greet all the experts first! I wish you all good work...I am a junior student at Hangzhou Dianzi University. I think I have good skills in micro...; 破茧佼龙 Power technology

Live Review: June 28th Datang NXP Semiconductors | Battery Management Chip Solution Design and Precautions: Live broadcast time: June 28 (Tuesday) 10:00-11:30 amLive broadcast topic: Battery management chip solution design and precautionsWatch replay: Click to watch Courseware Download Questions and Answers...; EEWORLD社区 Power technology

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components