ICS84427
C
RYSTAL
-
TO
-LVDS
I
NTEGRATED
F
REQUENCY
S
YNTHESIZER
/F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS84427 is a Crystal-to-LVDS Frequency
Synthesizer/Fanout Buffer. The output frequency can be
programmed using the frequency select pins. The low phase
noise characteristics of the ICS84427 make it an ideal clock
source for 10 Gigabit Ethernet, 10 Gigabit Fibre Channel, OC3
and OC12 applications.
F
EATURES
•
Six LVDS outputs
•
Crystal oscillator interface
•
Output frequency range: 77.76MHz to 625MHz
•
Crystal input frequency: 19.44MHz, 25MHz or 25.5MHz
•
RMS phase jitter at 155.52MHz, using a 19.44MHz crystal
(12kHz to 20MHz): 3.4ps (typical)
Phase noise:
Offset
Noise Power
100Hz ................. -95 dBc/Hz
1kHz ............... -110 dBc/Hz
10kHz ............... -120 dBc/Hz
100kHz ............... -121 dBc/Hz
•
3.3V supply voltage
•
0°C to 70°C ambient operating temperature
•
Available in both standard and lead-free RoHS-compliant
packages
F
UNCTION
T
ABLE
Inputs
F_XTAL
X
19.44MHz
19.44MHz
19.44MHz
19.44MHz
25MHz
25MHz
25MHz
25MHz
25.5MHz
MR
1
0
0
0
0
0
0
0
0
0
F_SEL2
X
1
1
1
1
0
0
0
0
0
F_SEL1 F_SEL0
X
0
0
1
1
0
0
1
1
0
X
0
1
0
1
0
1
0
1
1
Output
Frequency
F_OUT
LOW
77.76MHz
155.52MHz
311.04MHz
622.08MHz
78.125MHz
156.25MHz
312.5 MHz
625MHz
159.375MHz
B
LOCK
D
IAGRAM
XTAL_IN
P
IN
A
SSIGNMENT
0
1
6
Output
Divider
OSC
XTAL_OUT
PLL
/
6
/
Q0:Q5
nQ0:nQ5
Feedback
Divider
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
DD
F_SEL0
F_SEL1
MR
XTAL_IN
XTAL_OUT
F_SEL2
V
DDA
V
DD
PLL_SEL
GND
V
DD
ICS84427
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
F_SEL2 MR
PLL_SEL
F_SEL1
F_SEL0
84427CM
www.idt.com
1
REV. B JULY 27, 2010
ICS84427
C
RYSTAL
-
TO
-LVDS
I
NTEGRATED
F
REQUENCY
S
YNTHESIZER
/F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5, 6
7, 8
9, 10
11, 12
13, 16, 24
14
15
17
18
19,
20
21
22
23
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
V
DD
GND
PLL_SEL
V
DDA
F_SEL2
XTAL_OUT,
XTAL_IN
MR
F_SEL1
F_SEL0
Input
Power
Input
Input
Pullup
Pullup
Type
Output
Output
Output
Output
Output
Output
Power
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Core supply pins.
Power supply ground.
Selects between the PLL and cr ystal inputs as the input to the dividers.
When HIGH, selects PLL. When LOW, selects XTAL_IN and
XTAL_OUT. LVCMOS / LVTTL interface levels.
Analog supply pin.
Input
Input
Input
Feedback frequency select pin. LVCMOS/LVTTL interface levels.
Cr ystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs
Pulldown
nQx to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels.
Pullup
Output frequency select pin. LVCMOS/LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
84427CM
www.idt.com
2
REV. B JULY 27, 2010
ICS84427
C
RYSTAL
-
TO
-LVDS
I
NTEGRATED
F
REQUENCY
S
YNTHESIZER
/F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
50°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.72
Typical
3.3
3.3
Maximum
3.465
V
DD
300
30
Units
V
V
mA
mA
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
MR, F_SEL1
PLL_SEL,
F_SEL0, F_SEL2
MR, F_SEL1
PLL_SEL,
F_SEL0, F_SEL2
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IL
Input Low Current
T
ABLE
3C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.3
1.45
Test Conditions
Minimum
375
Typical
475
Maximum
575
50
1.6
50
Units
mV
mV
V
mV
84427CM
www.idt.com
3
REV. B JULY 27, 2010
ICS84427
C
RYSTAL
-
TO
-LVDS
I
NTEGRATED
F
REQUENCY
S
YNTHESIZER
/F
ANOUT
B
UFFER
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
19.44
Test Conditions
Minimum
Typical Maximum
25.5
50
7
1
Units
MHz
Ω
pF
mW
Fundamental
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
F
OUT
tjit(Ø)
tjit(cc)
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Cycle-to-Cycle Jitter ; NOTE 2
Output Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
47
155.52MHz,
(Integration Range: 12kHz-20MHz)
156.25MHz,
(Integration Range: 12kHz-20MHz)
Test Conditions
Minimum
77.76
3.4
3.1
36
85
600
52
1
Typical
Maximum
625
Units
MHz
ps
ps
ps
ps
ps
%
ms
t
sk(o)
t
R /
t
F
odc
t
LOCK
PLL Lock Time
See Parameter Measurement Information section.
NOTE 1: See Phase Noise Plots.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
84427CM
www.idt.com
4
REV. B JULY 27, 2010
ICS84427
C
RYSTAL
-
TO
-LVDS
I
NTEGRATED
F
REQUENCY
S
YNTHESIZER
/F
ANOUT
B
UFFER
T
YPICAL
P
HASE
N
OISE
0
-10
-20
-30
-40
-50
-60
-70
AT
155.52MH
Z
➤
SONET Filter
155.52MHz
RMS Phase Noise Jitter
12kHz to 20MHz = 3.4ps (typical)
P
HASE
N
OISE
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
(
dBc
)
H
Raw Phase Noise Data
Z
➤
1k
T
YPICAL
P
HASE
N
OISE
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
➤
10Gb Ethernet Filter
➤
Phase Noise Result by adding a
SONET Filter to raw data
10k
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
AT
156.25MH
Z
156.25MHz
RMS Phase Noise Jitter
12kHz to 20MHz = 3.1ps (typical)
P
HASE
N
OISE
( )
dBc
H
Z
Raw Phase Noise Data
➤
➤
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
84427CM
www.idt.com
5
REV. B JULY 27, 2010
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