FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer
Datasheet
8433625
General Description
The 8433625 is a 3 differential output LVPECL Synthesizer designed
to generate Ethernet reference clock frequencies. Using a 25MHz or
26.041666MHz, 18pF parallel resonant crystal, the following
frequencies can be generated based on the settings of 4 frequency
select pins (DIV_SELA[1:0], DIV_SELB[1:0]): 625MHz, 312.5MHz,
156.25MHz, and 125MHz. The 8433625 has 2 output banks, Bank A
with 1 differential LVPECL output pair and Bank B with 2 differential
LVPECL output pairs.
The two banks have their own dedicated frequency select pins and
can be independently set for the frequencies mentioned above. The
8433625 uses IDT’s 3
rd
generation low phase noise VCO technology
and can achieve 1ps or lower typical rms phase jitter, easily meeting
Ethernet jitter requirements. The 8433625 is packaged in a small
24-pin TSSOP package.
Features
•
•
•
•
•
•
•
•
Three 3.3V LVPECL outputs on two banks, A Bank with one
LVPECL pair and B Bank with 2 LVPECL output pairs
Using a 25MHz or 26.041666 crystal, the two output banks can be
independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
VCO range: 520MHz – 680MHz
RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.3ps (typical)
Full 3.3V supply mode
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
DIV_SELB0
VCO_SEL
MR
V
CCO_A
QA
nQA
OEB
OEA
FB
_DIV
V
CCA
V
CC
DIV_SELA0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIV_ SELB1
V
CCO_B
QB0
nQB0
QB1
nQB1
XTAL _SEL
REF_ CLK
XTAL _IN
XTAL _OUT
V
EE
DI V_SELA1
8433625
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
©2016 Integrated Device Technology, Inc.
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Revision B, February 2, 2016
8433625 Datasheet
Block Diagram
OEA
DIV_SELA[1:0]
VCO_SEL
XTAL_SEL
Pullup
2
Pullup: Pulldown
Pullup
Pullup
REF_CLK
Pulldown
00 = ÷1
01 = ÷2
10 = ÷4
(default)
11 = ÷5
QA
nQA
0
XTAL_IN
Xtal
Osc
0
PD +
LPF
FemtoClock VCO
1
1
00 = ÷1
01 = ÷2
10 = ÷4
11 = ÷5
(default)
QB0
nQB0
QB1
nQB1
XTAL_OUT
0 = ÷25
(default)
1 = ÷24
FB_DIV
DIV_SELB[1:0]
Pulldown
Pullup
2
MR
OEB
Pulldown
Pullup
©2016 Integrated Device Technology, Inc.
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Revision B, February 2, 2016
8433625 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1
Name
DIV_SELB0
Input
Type
Pullup
Description
Division select pin for Bank B. Default = HIGH. LVCMOS/LVTTL interface levels.
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
REF_CLK (depending on XTAL_SEL setting) are passed directly to the output
dividers. Has an internal pullup resistor so the PLL is not bypassed by default.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing
the true outputs Qx to go low and the inverted outputs nQx to go high. When logic
LOW, the internal dividers and the outputs are enabled. Has an internal pulldown
resistor so the power-up default state of outputs and dividers are enabled.
LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVPECL interface levels.
Output enable Bank B. Active High output enable. When logic HIGH, the output pair on
Bank B is enabled. When logic LOW, the output pair drives differential Low
(QBx = Low, nQBx = High). Has an internal pullup resistor so the default power-up
state of outputs are enabled. LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH, the output pair on
Bank A is enabled. When logic LOW, the output pair drives differential Low (QA = Low,
nQA = High). Has an internal pullup resistor so the default power-up state of outputs
are enabled. LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set for ÷25. When
HIGH, the feedback divider is set for ÷24. LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Pulldown
Pullup
Division select pin for Bank A. Default = LOW. LVCMOS/LVTTL interface levels.
Division select pin for Bank A. Default = HIGH. LVCMOS/LVTTL interface levels.
Negative supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit with a
single-ended reference clock.
Pulldown
Single-ended reference clock input. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended REF_CLK or crystal interface.
Has an internal pullup resistor so the crystal interface is selected by default.
LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pin for Bank B outputs.
Pullup
Division select pin for Bank B. Default = HIGH. LVCMOS/LVTTL interface levels.
2
VCO_SEL
Input
Pullup
3
MR
Input
Pulldown
4
5, 6
V
CCO_A
QA, nQA
Power
Output
7
OEB
Input
Pullup
8
OEA
Input
Pullup
9
10
11
12
13
14
15,
16
FB_DIV
V
CCA
V
CC
DIV_SELA0
DIV_SELA1
V
EE
XTAL_OUT,
XTAL_IN
REF_CLK
Input
Power
Power
Input
Input
Power
Input
Pulldown
17
Input
18
19, 20
21, 22
23
24
XTAL_SEL
nQB1, QB1
nQB0, QB0
V
CCO_B
DIV_SELB1
Input
Output
Output
Power
Input
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
©2016 Integrated Device Technology, Inc.
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Revision B, February 2, 2016
8433625 Datasheet
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Tables
Table 3A. Bank A and Bank B Frequency Table
Inputs
Crystal Frequency
(MHz)
25
25
25
25
26.041666
26.041666
26.041666
26.041666
DIV_SELA1,
DIV_SELB1
0
0
1
1
0
0
1
1
DIV_SELA0,
DIV_SELB0
0
1
0
1
0
1
0
1
Feedback
Divider
25
25
25
25
24
24
24
24
Bank A, Bank B
Output Divider
1
2
4
5
1
2
4
5
M/N
Multiplication
Factor
25
12.5
6.25
5
24
12
6
4.8
QA, nQA,
QB[0:1], nQB[0:1]
Output Frequency
(MHz)
625
312.5
156.25
125
625
312.5
156.25
125
FB_DIV
0
0
0
0
1
1
1
1
Table 3C. Output Bank Configuration Select Function Table
Inputs
DIV_SELA1
0
0
1
1
DIV_SELA0
0
1
0
1
Bank A
Output Divider
1
2
4 (default)
5
Inputs
DIV_SELB1
0
0
1
1
DIV_SELB0
0
1
0
1
Bank B
Output Divider
1
2
4
5 (default)
Table 3D. Feedback Divider Configuration Select Function Table
Inputs
FB_DIV
0
1
Feedback Divide
25 (default)
24
©2016 Integrated Device Technology, Inc.
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Revision B, February 2, 2016
8433625 Datasheet
Disabled
REF_CLK
Enabled
OEA, OEB
nQA0, nQBx
QA0, QBx
Figure 1. OE Timing Diagram
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
82.3C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
CC
= V
CCO_A
= V
CCO_B
= 3.3V ± 0.3V, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
V
CCO_A,
V
CCO_B
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.0
V
CC
– 0.25
3.0
Typical
3.3
3.3
3.3
Maximum
3.6
V
CC
3.6
125
25
Units
V
V
V
mA
mA
©2016 Integrated Device Technology, Inc.
5
Revision B, February 2, 2016
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