TLP7920,TLP7920F
Photocouplers
Optically Isolation Amplifiers
TLP7920,TLP7920F
1. Applications
•
•
Motor phase and rail current sensing
Power inverter current and voltage sensing
2. General
The TLP7920 and TLP7920F of isolation amplifiers is designed for current sensing in electronic motor drives. In
a typical implementation, motor currents flow through an external resistor and the resulting analog voltage drop
is sensed by the TLP7920 or TLP7920F.
3. Features
(1)
(2)
(3)
(4)
(5)
Output side supply voltage: 3.0 to 5.5 V
Output side supply current: 6.2 mA (typ.)
Operating temperature range: -40 to 105
Common-mode transient immunity: 15 kV/µs (min)
Safety standards
UL-approved: UL1577, File No.E67349
cUL-approved: CSA Component Acceptance Service No.5A File No.E67349
VDE-approved: EN60747-5-5, EN60065 or EN60950-1 (Note 1)
Note 1: When a VDE approved type is needed, please designate the Option (D4)
(D4).
Start of commercial production
©2016 Toshiba Corporation
1
2015-09
2016-05-23
Rev.2.0
TLP7920,TLP7920F
4. Packaging (Note)
TLP7920
TLP7920(LF1,TP1)
TLP7920(LF5,TP5)
11-10C4S
11-10C401S
11-10C405S
TLP7920F
TLP7920F(LF4,TP4)
11-10C402S
11-10C404S
Note:
Through-hole type: TLP7920, TLP7920F
Lead forming option: (LF1),(LF4),(LF5)
Taping option: (TP1),(TP4),(TP5)
©2016 Toshiba Corporation
2
2016-05-23
Rev.2.0
TLP7920,TLP7920F
5. Pin Assignment
5.1. Pin Functions
Pin No.
1
2
3
4
5
6
7
8
Symbol
V
DD1
V
IN+
V
IN-
GND1
GND2
V
OUT-
V
OUT+
V
DD2
Description
Input side supply voltage
Positive input
Negative input
Input side ground
Output side ground
Negative output
Positive output
Output side supply voltage
6. Internal Circuit (Note)
Note:
A 0.1
µF
bypass capacitor must be connected between 1 and 4 pins and between 5 and 8 pins.
7. Principle of Operation
7.1. Mechanical Parameters
Characteristics
Creepage distances
Clearance
Internal isolation thickness
7.62-mm Pitch
TLP7920
7.0 (min)
7.0 (min)
0.4 (min)
10.16-mm Pitch
TLP7920F
8.0 (min)
8.0 (min)
0.4 (min)
Unit
mm
©2016 Toshiba Corporation
3
2016-05-23
Rev.2.0
TLP7920,TLP7920F
8. Absolute Maximum Ratings (Note) (Unless otherwise specified, T
a
= 25
)
Characteristics
Supply Voltages
Steady-state input voltages
Two-second transient input voltages
Input power dissipation
Output voltages
Output power dissipation
Operating temperature
Storage temperature
Lead soldering temperature
Isolation voltage
(10 s)
AC, 60 s, R.H.
≤
60 %
Symbol
V
DD1
, V
DD2
V
IN+
, V
IN-
V
IN+
, V
IN-
P
D
V
OUT+
, V
OUT-
P
O
T
opr
T
stg
T
sol
BV
S
(Note 2)
(Note 3)
(Note 1)
(Note 1)
Note
Rating
-0.5 to 6
-0.5 to V
DD1
+ 0.5
-0.5 to 6
72
-0.5 to 6
60
-40 to 105
-55 to 125
260
5000
mW
V
mW
Vrms
Unit
V
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note: Ceramic capacitors (0.1
µF)
should be connected between 1 and 4 pins and between 5 and 8 pins to stabilize
the operation. Otherwise, this photocoupler may not switch properly. The bypass capacitors should be placed
as close as possible to each pin.
Note 1: Input power dissipation derating(T
a
≥
114.2
):
-6.7 mW/
Output power dissipation derating(T
a
≥
116.0
):
-6.7 mW/
Note 2:
≥
2 mm below seating plane.
Note 3: This device is considered as a two-terminal device: Pins 1, 2, 3 and 4 are shorted together, and pins 5, 6, 7
and 8 are shorted together.
Note:
9. Recommended Operating Conditions (Note)
Characteristics
Input side supply voltage
Output side supply voltage
Analog input voltage
Ambient temperature
Symbol
V
DD1
V
DD2
V
IN+
, V
IN-
T
a
(Note 1),
(Note 2)
Note
Min
4.5
3.0
-200
-40
Typ.
5
Max
5.5
5.5
200
105
mV
Unit
V
Note:
The recommended operating conditions are given as a design guide necessary to obtain the intended
performance of the device. Each parameter is an independent value. When creating a system design using
this device, the electrical characteristics specified in this datasheet should also be considered.
Note 1: FSR =
±300
mV
Note 2: When either V
IN+
or V
IN-
or both are equal to or greater than V
DD1
- 2 V (e.g., if V
DD1
= 5 V, when V
IN+
and/or
V
IN-
are equal to or greater than 5 V - 2 V = 3 V), isolation amplifiers go into one of the test modes. Do not
raise either V
IN+
or V
IN-
above this voltage to keep the device in functional mode.
©2016 Toshiba Corporation
4
2016-05-23
Rev.2.0
TLP7920,TLP7920F
10. Electrical Characteristics
10.1. DC Characteristics (Unless otherwise specified, T
a
= -40 to 105
,
V
DD1
= 4.5 to 5.5 V, V
DD2
= 3.0 to 5.5 V, V
IN+
= -200 to 200 mV, V
IN-
= 0 V)
Characteristics
Input offset voltage
Input offset voltage drift vs ambient
temperature
Symbol
V
OS
|dV
OS
/dT
a
|
Note
Test Condition
T
a
= 25
Min
-0.7
(Note 1) T
a
= 25
(Note 1) T
a
= 25
(Note 1) T
a
= 25
(Note 2) V
IN+
= -200 to 200 mV,
T
a
= 25
(Note 2) V
IN+
= -100 to 100 mV,
T
a
= 25
V
IN+
= 400 mV, T
a
= 25
V
IN+
= -400 mV, T
a
= 25
V
IN+
= 0 V, T
a
= 25
V
IN+
= 0 V
V
IN+
= 0 V
-1
Typ.
0.73
3
120
0.00012
0.02
0.00007
0.01
2.497
0.0009
80
-0.055
8.6
6.2
80
Max
2.1
10
0.13
0.06
12
10
dB
µA
mA
mA
kΩ
V/V/
%
%/
%
V
Unit
mV
µV/
µV/V
V/V
Input offset voltage drift vs input side |dV
OS
/dV
DD1
|
supply voltage
Gain (Rank B)
Gain (Rank A)
Gain (None)
Gain drift vs ambient temperature
V
OUT
non-linearity (±200 mV)
G
0
G
1
G
3
|dG/dT
a
|
NL
200
V
OUT
non-linearity (±200 mV) drift vs |dNL
200
/dT
a
|
ambient temperature
V
OUT
non-linearity (±100 mV)
High-level output voltage
Low-level output voltage
Input common-mode rejection ratio
Input bias current
Input side supply current (V
DD1
)
Output side supply current (V
DD2
)
Equivalent input resistance
NL
100
V
OH
V
OL
CMRR
IN
I
IN+
I
DD1
I
DD2
R
IN
Note 1: See Chapter 10.1.1 for gain rank values.
Note 2: The slope of the optimum line is derived by the method of least squares between differential input voltage
(V
IN+
- V
IN-
) and differential output voltage (V
OUT+
- V
OUT-
). Nonlinearity is defined as a fraction of the half of
the peak-to-peak value of differential output voltage deviation divided by the full-scale differential output voltage
(OVR).
10.1.1. Gain Rank (Note) (Unless otherwise specified, T
a
= 25
)
Rank
None (±3 %)
Rank A (±1 %)
Rank B (±0.5 %)
Gain Rank Marking
Blank, A, B
A, B
B
(Min)
7.95
8.12
8.16
Gain
(Typ.)
8.2
8.2
8.2
(Max)
8.44
8.28
8.24
Unit
V/V
Note:
Note:
The gain is defined as the slope of the optimum line derived by the method of
least squares between differential input voltage (V
IN+
- V
IN-
) and differential output
voltage (V
OUT+
- V
OUT-
) in the recommended voltage range.
Specify both the part number and a rank in this format when ordering.
Example: TLP7920(B,F(O
For safety standard certification, however, specify the part number alone.
Example: TLP7920(B,F(O
→
TLP7920
©2016 Toshiba Corporation
5
2016-05-23
Rev.2.0
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